مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA Implementation of MIMO System for Symbol-Wavelength-Spaced Antennas
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

For Line-of-Sight (LOS) radio channels, recent research shows that in order to improve effectively the performance of a Multi-input Multi-output (MIMO) system, the antenna elements at the receiver must be separated on the scale of a symbol wavelength ([speed of light]/[symbol rate]). The main focus of this thesis was to design, implement and test a two-by-two (2X2) system based on that separation. The system was implemented on a single Field Programmable Gate Array (FPGA) board. The adaptive Space-Time (ST) receiver in the system includes a Least Mean Square (LMS) algorithm to adapt the coefficients. The system was developed using Altera Quartus II software and Verilog HDL was used as the coding language. The system was debugged and tested for convergence using MATLAB and the Altera SignalTap II Logic Analyzer software. The results indicate that the system converges successfully. The system’s converged coefficients show selected ranges of zeros or small values

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA-based Laser Stabilisation using Modulation Transfer Spectroscopy
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

This project investigated the closed-loop frequency stabilisation of a diode laser using a heterodyne scheme known as modulation transfer spectroscopy. FPGA-based digital signal processing was used in place of a standard analogue approach. By digitally synthesising the driving signal for an acousto-optic modulator, unprecedented control over the modulation transfer spectroscopy error signal was achieved. Digital mixing and loop ltering provided performance comparable to an analogue approach. A control bandwidth of 150 kHz was achieved, limited by the diode laser controller rather than the digital system

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Abstracting the Hardware / Software Boundary through a Standard System Support Layer and Architecture
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

Reconfigurable computing is often lauded as having the potential to bridge the performance gap between computational needs and computational resources. Although numerous successes exist, difficulties persist bridging the CPU/FPGA boundary due to relegating hardware and software systems as separate and inconsistent computational models. Alternatively, the work presented in this thesis proposes using parallel programming models to abstract the CPU/FPGA boundary. Computational tasks would exist either as traditional CPU bound threads or as custom hardware threads running within the FPGA. Achieving an abstract parallel programming model that spans the hardware/software boundary depends on: extending an existing software parallel programming model into hardware, abstracting communication between hardware and software tasks, and providing equivalent high-level language constructs for hardware tasks. This thesis demonstrates that a shared memory multi-threaded programming model with high-level language semantics may be extended to hardware, consequently abstracting the hardware/software boundary. The research for this thesis was conducted in three phases, and used the KUdeveloped Hybridthread Computational Model as its base operating system and platform. The first phase extended the semantics of a running thread to a new, independent and standard hardware system support layer known as the Hardware Thread Interface (HWTI). In this phase hardware threads are given a standard interface providing communication between the hardware thread and system. The second phase of the research extended and augmented the initial design to support a meaningful abstraction. Mechanisms in this phase include globally distributed local memory, a standard function call stack including support for recursion, high level language semantics, and a remote procedure call model. The third phase evaluated the HWTI by comparing the semantic and implementation differences

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A 2-D Processor Array for Massively Parallel Image Processing on FPGA
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

The concept of introducing image processing logic within the spatial gaps of an array of photodiodes is the key factor behind the presented work. A two dimensional massively parallel image processing paradigm based on 8×8 pixel neighborhood digital processors has been designed. A low complexity processor array architecture along with its instruction set has been designed and fully verified on a FPGA platform. Various image processing tests have been run on the FPGA platform to demonstrate the functionality of a design that uses 12 parallel processors. The test results indicate that the architecture is scalable to support high frame rates while allowing for flexible processing due to inherent programmability at a high level. The gate level logic synthesis results of the processor targeting a 0.13 μm CMOS technology indicates a low silicon area complexity, allowing for image sensor integration

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA-based Smart NIR Camera
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

Road conditions are a critical issue for road users as, if not given sufficient attention, they may threaten users’ lives. The environmental parameters, such as snowy, icy, dry and wet, are important in relation to the condition of roads. This is particularly true in relation to the northern regions and greatest concern should be in relation to snowy and icy situations. In this thesis, a system based on an InGaAs area scan sensor utilizes NIR technology to detect water or ice on the road so as to enable drivers to avoid slippery road conditions. The conditions caused by freezing water on road surface are particularly dangerous and are not easy to observe and it is hope that this project will boost traffic safety. The system is able to assist road maintenance personnel in forecasting and detecting slippery road conditions during winter road maintenance (WRM). The system, which is based on FPGA, has functionalities that display the captured images on an HDMI monitor and send the images to the software on a host PC via the UART protocol. An interface board, which carries the sensor and which connects to the FPGA board, is developed for NIR sensor. VHDL implementation and PC software design are the works included in the project. Besides, this device is exploited utilizing InGaAs image sensor. According to its features, it can be applied in other applications which will also be discussed. Finally, experiments are conducted in order to investigate the system’s operation with the variation of temperature

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A Multiple-FPGA Parallel Computing Architecture for Real-time Simulation of Deformable Objects
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

In recent years there has been a growing interest in computer-based surgical planning, virtual-reality enabled training of medical procedures, and computer gaming all involving non-rigid deformable objects. High-fidelity simulations of haptic interaction with deformable objects is computationally demanding. The Finite Element Method (FEM) is known to produce relatively accurate solution for continuum mechanics-based models of soft-object deformation. Linear elastic FE models require solving a large sparse system of equations. The solution accuracy can be improved by increasing the resolution of the finite element mesh resulting in a larger number of equations and hence greater computational complexity. Depending on the mechanical characteristics of the soft-object, to maintain stability and high fidelity in haptic interaction, the update rate should be in the range of 100-1000Hz. This, for example, means that for a moderately-sized three-dimensional mesh of 6000 nodes, a set of 18000 linear equations must be solved within 1-10ms. In this thesis, hardware-based parallel computing is proposed for finite-element (FE) analysis of soft-object deformation models. In particular, a distributed implementation of the (CG) algorithms on N Field Programmable Gate Array (FPGA) devices connected in a ring configuration is developed. This Parallel architecture can be utilized to solve the large system of equations arising from FE models at high update rates required for stable haptic interaction. Massive parallelization of the computations is achieved by customizing the hardware architecture to the problem at hand and employing a large number of adaptive fixed-point computing units in parallel. The proposed hardware architecture satisfies three important criteria: (i) it meets the haptic rendering timing constraint by enabling an update rate of 400Hz; (ii) it attempts to simulate as many nodes as possible, given the available resources on the FPGA devices employed in this work and (iii) it is scalable both within an FPGA and also across multiple FPGA devices

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Embedded Network Firewall on FPGA
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

The Internet has profoundly changed today’s human being life. A variety of information and online services are offered by various companies and organizations via the Internet. Although these services have substantially improved the quality of life, at the same time they have brought new challenges and difficulties. The information security can be easily tampered by many threats from attackers for different purposes. A catastrophe event can happen when a computer or a computer network is exposed to the Internet without any security protection and an attacker can compromise the computer or the network resources for destructive intention. The security issues can be mitigated by setting up a firewall between the inside network and the outside world. A firewall is a software or hardware network device used to enforce the security policy to the inbound and outbound network traffic, either installed on a single host or a network gateway. A packet filtering firewall controls the header field in each network data packet based on its configuration and permits or denies the data passing thorough the network. The objective of this thesis is to design a highly customizable hardware packet filtering firewall to be embedded on a network gateway. This firewall has the ability to process the data packets based on: source and destination TCP/UDP port number, source and destination IP address range, source MAC address and combination of source IP address and destination port number. It is capable of accepting configuration changes in real time. An Altera FPGA platform has been used for implementing and evaluating the network firewall

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA Control of Power Systems in Graduate Student Laboratories
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

The Department of Electrical and Computer Engineering at the Naval Postgraduate School (NPS) continuously develops new design and education resources for students. One area of focus for students in the Power Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA) control of power electronics. Utilizing Mathworks® and XILINX® software to interface the FPGA with power converters, students gain experience with digital design, simulation, and hardware testing. This thesis focuses on the design, implementation and testing of a Student Design Center (SDC) employing an FPGA based digital controller. This thesis especially concentrates on the hardware interface between the FPGA and the power electronics and the development of laboratory procedures for students utilizing the design center

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of Parallel FIR Filter
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

The diploma thesis deals with design of interpolated FIR filter on FPGA. The thesis is focused on reduction of power consumption and occupied silicon space, needed for implementation of filter in FPGA. The results are IP macros of simple and interpolated FIR filter that are full configurable using generic parameters. Both macros were verified in a verification environment which consists of test blocks (VHDL) and a comparative model (Matlab). A design of interpolated FIR filter is described in this work. Next there are described final designs of the IP macros, results and process of the verification, implementation and gate-level verification. In this work is also described an application which can be used for design of interpolated FIR filters

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: BitMaT: Bitstream Manipulation Tool for Xilinx FPGAs
نوع فایل: پایان نامه
سال انتشار: 2005
چکیده:

With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: HDL Implementation of CCSDS Standards
نوع فایل: پایان نامه
سال انتشار: 2013
چکیده:

Communication to and from a satellite is a complicated endeavor. The purpose of this master thesis is to design a communications system for small satellites that will run in a Field Programmable Gate Array for use on satellites. The communication system is developed in preparation for new standards and recommendations from the European Cooperation for Space Standardization that will take into account new communications protocols from the Consultative Committee for Space Data Systems. The existing standards and recommendations that describe the current version of protocols were thoroughly studied. The communication system design is based on the information gleaned for these documents, such as the structure of frames and packets. The hardware for the communication system is designed in the hardware description language Verilog. This code is intended to be loaded into a Field Programmable Gate Array. The communication system is required to be able to receive and decode telecommands and extract packets out of the telecommand frames. The commands in these packets should be either executed or sent on to the connected CPU. The system should also be able to construct packets from data sent from the CPU, place the packets in frames, encode the frames and send them as telemetry. The code is simulated using a multitude of test messages and the results were reviewed. Finally synthesis of the code is done to see if it can function in the Field Programmable Gate Array. The final communication system design fulfils all the demands set by the standards and recommendations. The system can detect all the errors that it is designed to detect and the design fits nicely inside the Microsemi ProASIC3E A3PE3000 Field Programmable Gate Array

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design of an FPGA Based JTAG Recorder for Use in Production of IPTV Set-Top Boxes
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

This thesis evaluates the possibility to replace the manufacturer dependent JTAG device used in the production tests of IPTV set-top boxes for storing the boot loader in the main memory in order to start the box for the first time. An FPGA based prototype was built in order to see if it is possible to record the JTAG signals, to an external DDR SDRAM, without understanding them and be able to perform a delayed playback resulting in the same behavior as with the original JTAG device. Overall the thesis was successful and it shows that it is in fact feasible to create a JTAG recorder based on an FPGA. A lot of data is used for storing the sequence though so the use of a fast memory is crucial. However in this thesis the speed of both the recording and the delayed playback was reduced in order to work properly

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An FPGA Implementation for a High-Speed Optical Link with a PCIe Interface
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

This thesis describes the design and implementation of an optical fiber based high speed interface between two computers. The system is particular in that the data transits in a Field Programmable Gate Array (FPGA) situated between each computer and the optical fiber link. The measured full duplex speed for exchanging data between two C programs running on two different computers is over 8Gbit/s, including encoding, protocol and software overhead. This design is suited for applications requiring high bandwidth between two computers, and since an FPGA sees all the data being exchanged, it can be used as a fast and flexible data processing tool: Error correction, debug support, data analysis, encryption and compression are all possible uses where the FPGA can save the Central Processing Unit (CPU) an important amount of computing cycles

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Energy Efficiency Analysis and Implementation of AES on an FPGA
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique