عدم تطابق برنامه پروگرم شده با شبیه سازی

[kooshkestani]

سلام به دوستان
برنامه ای که در ذیل مشاهده میکنید در شبیه سازی به طور کامل جواب میده ولی با cpld که پروگرم میکنم جواب نمیگیرم مشکل اصلی clk_enable است که اونجوری که باید، بهش عکس العمل نشون نمیده

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fm is
Port ( clk_enable : in STD_LOGIC;
clk : in STD_LOGIC;
micro_wave : in STD_LOGIC;
data_clock : in STD_LOGIC;
int : out STD_LOGIC;
data : out STD_LOGIC_VECTOR (7 downto 0));
end fm;

architecture Behavioral of fm is


signal twomega_clk_counter:std_logic_vector(23 downto 0):=x"000000"; --should be initialized for counting to be correct
signal counters_enable:bit:='0';
signal data_index:integer range 0 to 25:=0;
signal int_sig:std_logic:='0';
---------------------------------for test
--signal divider:std_logic_vector(24 downto 0):="0000000000000000000000000";
-----------------------------------------

begin



int<=int_sig;

twomega_clk_process:process (clk)
begin
if clk='1' and clk'event then
if counters_enable='1' then
twomega_clk_counter <= twomega_clk_counter + 1;
end if;
end if;
end process twomega_clk_process;


micro_wave_process:process (micro_wave)
variable micro_wave_pulse_counter:integer:=0;
begin
if (micro_wave='1' and micro_wave'event) then

if (counters_enable='1&#039 then

micro_wave_pulse_counter:=micro_wave_pulse_counter +1;
if micro_wave_pulse_counter=16384 then
counters_enable<='0';
int_sig<=not(int_sig);
end if;

elsif (clk_enable='1' and micro_wave_pulse_counter=0) then
counters_enable<='1';
end if;

end if;
end process micro_wave_process;

data_clock_process:process(data_clock)
begin
if (data_clock='1' and data_clock'event) then
data<=twomega_clk_counter(7+data_index downto data_index);
data_index<=data_index+8;
end if;
end process data_clock_process;
-------------------------------------------------for test
--process (clk)
--begin
-- if clk='1' and clk'event then
-- if clk_enable='1' then
-- divider <= divider + 1;
-- end if;
-- end if;
--end process;
--
-- data(4)<=divider(24);
-------------------------------------------------------


end Behavioral;