سلام
من دیتا شیت مگا 8 رو خوندم و دیدم نوشته
By default, the successive approximation circuitry requires an input clock frequency between
50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC
clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes
25 ADC clock cycles in order to initialize the analog circuitry.
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START
192
2486Z–AVR–02/11
ATmega8(L)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion
and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
In Free Running mode, a new conversion will be started immediately after the conversion completes,
while ADSC remains high. For a summary of conversion times
حالا چند تا سوال برام پیش اومده
نوشته حالت عادی 13 سیکل
حالت انتخابی 25 سیکل
حالا حالت عادی یعنی چی؟
یعنی هر پین adc 13 سیکل یا یک دور خوندن کامل کل adc ها 13 سیکل؟
حالا یه سوال دیگه کلاک روی 000 000 1 باشه و اگه 6 تا adc رو بخونیم هر کدوم چه مدت طول میکشه؟
من دیتا شیت مگا 8 رو خوندم و دیدم نوشته
By default, the successive approximation circuitry requires an input clock frequency between
50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC
clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes
25 ADC clock cycles in order to initialize the analog circuitry.
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START
192
2486Z–AVR–02/11
ATmega8(L)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion
and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
In Free Running mode, a new conversion will be started immediately after the conversion completes,
while ADSC remains high. For a summary of conversion times
حالا چند تا سوال برام پیش اومده
نوشته حالت عادی 13 سیکل
حالت انتخابی 25 سیکل
حالا حالت عادی یعنی چی؟
یعنی هر پین adc 13 سیکل یا یک دور خوندن کامل کل adc ها 13 سیکل؟
حالا یه سوال دیگه کلاک روی 000 000 1 باشه و اگه 6 تا adc رو بخونیم هر کدوم چه مدت طول میکشه؟
دیدگاه