مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

[حمید نجفی]

سلام
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[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

eBook

نام : Digital Logic and Microprocessor Design With VHDL

http://wdl.persiangig.com/pages/down...ng-2005%29.pdf

[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

Article

نام: FPGA IMPLEMENTATIONS OF HIGH THROUGHPUT SEQUENTIAL AND FULLY PIPELINED AES ALGORITHM
ژورنال: IJEE
سال چاپ: 2008

http://wdl.persiangig.com/pages/down...05-447-456.pdf

[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA


نام : FPGA Implementations of Neural Networks


http://wdl.persiangig.com/pages/down...Omondi2006.pdf

[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

Article

نام : An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection
ژورنال : JSTS
سال چاپ: 2012

http://wdl.persiangig.com/pages/down...me12_02_04.pdf

[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

Article

نام: Digital very-large-scale integration (VLSI) Hopfield neural network implementation on field programmable gate arrays (FPGA) for solving constraint satisfaction problems
ژورنال: JETR
سال چاپ: 2012

http://wdl.persiangig.com/pages/down...rinivasulu.pdf

[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

eBook

نام: Circuit Design with VHDL

http://wdl.persiangig.com/pages/down...h%252BVHDL.pdf

[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

Article

نام: JPEG Image Compression using FPGA with Artificial Neural Networks
ژورنال: IJET
سال چاپ: 2010

http://wdl.persiangig.com/pages/down...k/129-T264.pdf

[حمید نجفی]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

در مورد FFT با VHDL :
http://wdl.persiangig.com/pages/down...A/FFT-VHDL.pdf

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Watermarking FPGA Bitfile for Intellectual Property Protection
کنفرانس: Radioengineering
سال انتشار: 2012
چکیده:

Intellectual property protection (IPP) of hardware designs is the most important requirement for many Field Programmable Gate Array (FPGA) intellectual property (IP) vendors. Digital watermarking has become an innovative technology for IPP in recent years. Existing watermarking techniques have successfully embedded watermark into IP cores. However, many of these techniques share two specific weaknesses: 1) They have extra overhead, and are likely to degrade performance of design; 2) vulnerability to removing attacks. We propose a novel watermarking technique to watermark FPGA bitfile for addressing these weaknesses. Experimental results and analysis show that the proposed technique incurs zero overhead and it is robust against removing attacks

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Implementation of an FPGA-based Adaptive filter Single-User Receiver
نوع فایل: پایان نامه
سال انتشار: 1999
چکیده:

During the last decade, the wireless communications industry has grown rapidly. Driven by market demand, service providers are continuously looking for better systems. The main focus of continued research has been to increase the quality of services and system capacity. The Code Division Multiple Access (CDMA) cellular system had been proposed for use as a new standard for cellular telephone systems. A great deal of research has been conducted to develop receiver structures useful for CDMA systems. Traditional receivers such as the correlation and RAKE receivers are vulnerable to the near-far problem, i.e., the problem encountered when one received signal power is stronger than another. This problem is common in mobile environments. For single-user receivers, adaptive filtering techniques can be employed to alleviate multiple access interference and the near-far problem. In this thesis, an adaptive filter receiver is implemented on the FPGA-based configurable computing platform called GigaOps G900. By using FPGAs, designers can implement special-purpose signal processing architectures using specialized data paths, optimized sequencing, and pipelining while still providing some flexibility. This results in better overall system performance, resource utilization, and reduced power consumption

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A C-to-FPGA Solution for Accelerating Tomographic Reconstruction
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

Computed Tomography (CT) image reconstruction techniques represent a class of algorithms that are ideally suited for co-processor acceleration. The Filtered Backprojection (FBP) algorithm is one such popular CT reconstruction method that is computationally intensive but amenable to extensive parallel execution. We develop an FPGA accelerator for the critical backprojection step in FBP using a C-to-FPGA tool flow called Impulse C. We document the strategies that work well with Impulse C, and show orders of magnitude speedup over a software implementation of backprojection. We contrast the ease of use and performance of Impulse C against traditional HDL design, and demonstrate that Impulse C can achieve nearly the same performance as hand coded HDL while significantly reducing the design effort

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Enabling Development of OpenCL Applications on FPGA Platforms
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

FPGAs can potentially deliver tremendous acceleration in high-performance server and embedded computing applications. Whether used to augment a processor or as a stand-alone device, these reconfigurable architectures are being deployed in a large number of implementations owing to the massive amounts of parallelism offered. At the same time, a significant challenge encountered in their wide-spread acceptance is the laborious efforts required in programming these devices. The increased development time, level of experience needed by the developers, lower turns per day and difficulty involved in faster iterations over designs affect the time-to-market for many solutions. High-level synthesis aims towards increasing the productivity of FPGAs and bringing them within the reach software developers and domain experts. OpenCL is a specification introduced for parallel programming purposes across platforms. Applications written in OpenCL consist of two parts - a host program for initialization and management, and kernels that define the compute intensive tasks. In this thesis, a compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is presented. The flow uses Xilinx AutoESL tool to obtain the design specification for compute cores. An architecture provided integrates the cores with memory and host interfaces. The host program in the application is compiled and executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end flow that provides abstraction of hardware at the front-end

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Real Time Machine Vision on FPGA
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

In today's industry more and more automation is being introduced and computer vision plays a great role here. Normally these computer vision systems are implemented using a typical PC. As the complexity of a vision system increases, the frame rate at which the PC is capable of processing images real time decreases. This is due to the sequential operation mode of the CPU. We wish to examine whether typical low level vision algorithms could be implemented more efficiently on a parallel structure such as the FPGA. This report describes the hardware and software development of a real time machine vision system on an FPGA using FireWire for communication and image transfer. We have implemented frequently used low level vision algorithms, such as a general mask operation, median filter, Canny edge detection and blob detection. Most of the ideas for implementing the algorithms have been found in other papers except for blob detection which we have implemented in a new and efficient way and Canny edge detection were we use a median filter to remove noise instead of a Gaussian filter

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping
نوع فایل: پایان نامه
سال انتشار: 2013
چکیده:

As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devices on critical paths forces designers to reduce clock speed in order to meet timing. For an important and emerging class of applications that target energy-minimal operation at the cost of delay, the impact of variation-induced defects at very low voltages mandates the sizing up of transistors and operation at higher voltages to maintain functionality. With post-fabrication configurability, FPGAs have the opportunity to self-measure the impact of variation, determining the speed and functionality of each individual resource. Given that information, a delay-aware router can use slow devices on non-critical paths, fast devices on critical paths, and avoid known defects. By mapping each component individually and customizing designs to a component’s unique physical characteristics, we demonstrate that we can eliminate delay margins and reduce energy margins caused by variation. To quantify the potential benefit we might gain from component-specific mapping, we first measure the margins associated with parameter variation, and then focus primarily on the energy benefits of FPGA delay-aware routing over a wide range of predictive technologies (45 nm–12 nm) for the Toronto20 benchmark set. We show that relative to delay-oblivious routing, delay-aware routing without any significant optimizations can reduce minimum energy/operation by 1.72× at 22 nm. We demonstrate how to construct an FPGA architecture specifically tailored to further increase the minimum energy savings of component-specific mapping by using the following techniques: power gating, gate sizing, interconnect sparing, and LUT remapping. With all optimizations considered we show a minimum energy/operation savings of 2.66× at 22 nm, or 1.68–2.95× when considered across 45–12 nm. As there are many challenges to measuring resource delays and mapping per chip, we discuss methods that may make component-specific mapping more practical. We demonstrate that a simpler, defect-aware routing achieves 70% of the energy savings of delay-aware routing. Finally, we show that without variation tolerance, scaling from 16 nm to 12 nm results in a net increase in minimum energy/operation; component-specific mapping, however, can extend minimum energy/operation scaling to 12 nm and possibly beyond