مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: VERILOG Design and FPGA Prototype of a Nano-Controller System
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Many new fabrication technologies, from nanotechnology and MEMS to printed organic semiconductors, center on constructing arrays of large numbers of sensors, actuators, or other devices on a single substrate. The utility of such an array could be greatly enhanced if each device could be managed by a programmable controller and all of these controllers could coordinate their actions as a massively-parallel computer. Kentucky Architecture nanocontroller array with very low per controller circuit complexity can provide efficient control of nanotechnology devices. This thesis provides a detailed description of the control hierarchy of a digital system needed to build "nanocontrollers" suitable for controlling millions of devices on a single chip. A Verilog design and FPGA prototype of a nanocontroller system is provided to meet the constraints associated with a massively-parallel programmable controller system

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Using an FPGA-based Processing Platform in an Industrial Machine Vision System
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

This thesis describes the development of a commercial machine vision system as a case study for utilizing the Modular Reprogrammable Real-time Processing Hardware (MORRPH) board. The commercial system described in this thesis is based on a prototype system that was developed as a test-bed for developing the necessary concepts and algorithms. The prototype system utilized color linescan cameras, custom framegrabbers, and standard PCs to color-sort red oak parts (staves). When a furniture manufacturer is building a panel, very often they come from edge-glued paneled parts. These are panels formed by gluing several smaller staves together along their edges to form a larger panel. The value of the panel is very much dependent upon the “match” of the individual staves—i.e. how well they create the illusion that the panel came from a single board as opposed to several staves. The prototype system was able to accurately classify staves based on color into classes defined through a training process. Based on Trichromatic Color Theory, the system developed a probability density function in 3-D color space for each class based on the parts assigned to that class during training. While sorting, the probability density function was generated for each scanned piece, and compared with each of the class probability density functions. The piece was labeled the name of the class whose probability density function it most closely matched. A “best-face” algorithm was also developed to arbitrate between pieces whose top and bottom faces did not fall into the same classes. [1] describes the prototype system in much greater detail. In developing a commercial-quality machine vision system based on the prototype, the primary goal was to improve throughput. A Field Programmable Gate Array (FPGA)-based Custom Computing Machine (FCCM) called the MORRPH was selected to assume most of the computational burden, and increase throughput in the commercial system. The MORRPH was implemented as an ISA-bus interface card, with a 3 x 2 array of Processing Elements (PE). Each PE consists of an open socket which can be populated with a Xilinx 4000 series FPGA, and an open support socket which can be populated with support chips such as external RAM, math processors, etc. In implementing the prototype algorithms for the commercial system, a partition was created between those algorithms that would be implemented on the MORRPH board, and those that would be left as implemented on the host PC. It was decided to implement such algorithms as Field-Of-View operators, Shade Correction, Background Extraction, Gray-Scale Channel Generation, and Histogram Generation on the MORRPH board, and to leave the remainder of the classification algorithms on the host. By utilizing the MORRPH board, an industrial machine vision system was developed that has exceeded customer expectations for both accuracy and throughput. Additionally, the color-sorter received the International Woodworking Fair’s Challengers Award for outstanding innovation

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA Implementation of Blob Recognition
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Real-time embedded vision systems can be used in a wide range of applications and therefore the demand has been increasing for them. In this thesis, an FPGA-based embedded vision system capable of recognizing objects in real time is presented. The proposed system architecture consists of multiple Intellectual Properties (IPs), which are used as a set of complex instructions by an integrated 32-bit CPU Microblaze. Each IP is tailored specifically to meet the needs of the application and at the same time to consume the minimum FPGA logic resources. Integrating both hardware and software on a single FPGA chip, this system can achieve the real-time performance of full VGA video processing at 32 frames per second (fps). In addition, this work comes up with a new method called Dual Connected Component Labelling (DCCL) suitable for FPGA implementation

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: FPGA-based Smart Antenna Implementation
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

Adaptive beam formers for sensor arrays, are widely used in RADAR, SONAR and communications applications in order to increase the directivity of the sensor system to the target, while suppressing the interfering signals by adapting the radiation pattern of the antenna
array. A signal processing hardware accomplishes the beam forming by adjusting the weights of the sensor array system. Even though the hardware for similar applications have been generally preferred as a Digital Signal Processor (DSP), Field Programmable Gate Arrays (FPGA), have become a promising alternative, for various signal processing techniques, with increasing logic elements they include. In this manner, logic elements included in the FPGA can be arranged as distinct processors running concurrently, therefore signal processing algorithms running on distinct processors can be implemented by employing FPGA technology. Systolic arrays are processor arrays, that operate concurrently and pass data between the neighbor processors in order to perform complex functions. Optimal weight extraction based on systolic structures have been the subject of various researches for nearly two decades. In this thesis we propose a rectangular systolic structure for QR decomposition based recursive least squares algorithm for a minimum variance distortionless response beam former and a folding scheme for this systolic structure. Folding a systolic array reduces the die size of the hardware implementation, accordingly systolic arrays for larger sensor systems will be able to be implemented without employing a larger FPGA chip. In this thesis, the SystemC library is preferred for developing the necessary software and for the implementation of the algorithm on the hardware. The SystemC is accepted by IEEE as a standard for system development and simulation in 2006. The proposed systolic structure is then implemented on a FPGA based DSP Development board and the results are compared with the conventional systolic array based beam former hardware. This method can be applied to sensor array beam forming application

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: CRUSH: Cognitive Radio Universal Software Hardware
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

The FPGA is an integral component of a software defined radio (SDR) that provides the needed reconfigurability for dynamically adapting its transceiver and data processing functions. Because of the desire to process data faster and with less latency, researchers are looking at FPGA-based SDR. Our architecture, called CRUSH (Cognitive Radio Universal Software Hardware), is composed of a Xilinx ML605 connected to an Ettus USRP through a custom interface board, allowing flexible data transfer between them. In addition, we provide a framework that supports ease of use, independent programming on both devices, and integration with software running on the host. To demonstrate our platform we implemented spectrum sensing, a key step in determining channel availability before transmission in dynamic spectrum access networks. Spectrum sensing is implemented on CRUSH using FFTs for a 100x speedup; the complete sensing cycles is 10x faster than the same design without CRUSH. By reducing the load on the host and allowing a powerful FPGA extension for off-the-shelf devices, CRUSH enables advances in both protocol design and reconfigurable hardware targeting radio applications

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: FPGA Implementation of Robust Symmetrical Number System in High-Seed Folding ADCs
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Analog-To-Digital Converters (ADCs) are integral building blocks of most sensor and communication systems today. As the need for ADCs with faster conversion speeds and lower power dissipation increases, there is a growing motivation to reduce the number of power-consuming components by employing folding circuits to fold the input analog signal symmetrically, prior to quantization by high-speed comparators. These properties of low-power consumption, compactness, high-resolution and fast conversion speeds make folding ADCs an attractive concept to be used for defense applications, such as unmanned systems, direction-finding antenna architectures and system-on-a-chip applications. In this thesis, a prototype of an optical folding ADC was implemented using the Robust Symmetrical Number System (RSNS). The architecture employs a three-dulus (Moduli 7, 8, 9) scheme to preprocess the antenna signal. This thesis focuses on the simulation and hardware implementation of this ADC architecture, including the bank of comparators and the RSNS-to-Binary Conversion within a Field Programmable Gate Array (FPGA), to achieve an eight-bit Dynamic Range of 133. This is then integrated with the front-end photonics implementation (designed under a separate thesis). Low frequency analyses of the results using a 1-kHz input signal indicate a 5.39 Effective Number of Bits (ENOB), a Signal-to-Noise Ratio plus Distortion (SINAD) of 34.21 dB, and a Total Harmonic Distortion (THD) of 61.68 dB

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Airblue: A Highly Configurable FPGA-based Platform for Wireless Network Research
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Over the past few years, researchers have developed many cross-layer wireless protocols to improve the performance of wireless networks. Experimental evaluations of these protocols require both high-speed simulations and real-time on-air experimentations. Unfortunately, radios implemented in pure software are usually inadequate for either because they are typically two to three orders of magnitude slower than commodity hardware. FPGA-based platforms provide much better speeds but are quite difficult to modify because of the way high-speed designs are typically implemented by trading modularity for performance. Experimenting with cross-layer protocols requires a flexible way to convey information beyond the data itself from lower to higher layers, and a way for higher layers to configure lower layers dynamically and within some latency bounds. One also needs to be able to modify a layer’s processing pipeline without triggering a cascade of changes. In this thesis, we discuss an alternative approach to implement a high-performance yet configurable radio design on an FPGA platform that satisfies these requirements. We propose that all modules in the design must possess two important design properties, namely latency-insensitivity and data-driven control, which facilitate modular refinements. We have developed Airblue, an FPGA-based radio, that has all these properties and runs at speeds comparable to commodity hardware. Our baseline design is 802.11g compliant and is able to achieve reliable communication for bit rates up to 24 Mbps. We show in the thesis that we can implement SoftRate, a cross-layer rate adaptation protocol, by modifying only 5.6% of the source code (967 lines). We also show that our modular design approach allows us to abstract the details of the FPGA platform from the main design, thus making the design portable across multiple FPGA platforms. By taking advantage of this virtualization capability, we were able to turn Airblue into a high-speed hardware software co-simulator with simulation speed beyond 20 Mbps

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of the biometric process in hardware like digital camera or scanners etc. To address such issues, a novel approach and its architecture in the framework of a digital camera, conceptualized as an SDC is presented. The SDC inserts biometric data into passport image with the aid of watermarking and encryption processes. The VLSI (very large scale integration) architecture of the functional units of the SDC such as watermarking and encryption unit is presented. The result of the hardware implementation of Rijndael advanced encryption standard (AES) and a discrete cosine transform (DCT) based visible and invisible watermarking algorithm is presented. The prototype chip can carry out simultaneous encryption and watermarking, which to our knowledge is the first of its kind. The encryption unit has a throughput of 500 Mbit/s and the visible and invisible watermarking unit has a max frequency of 96.31 MHz and 256 MHz respectively

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Design of an FPGA-based Array Formatter for CASA Phase-tilt Radar System
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Weather monitoring and forecasting systems have witnessed rapid advancement in recent years. However, one of the main challenges faced by these systems is poor coverage in lower atmospheric regions due to earth’s curvature. The Engineering Research Center for the Collaborative Adaptive Sensing of the Atmosphere (CASA) has developed a dense network of small low-power radars to improve the coverage of weather sensing systems. Traditional, mechanically-scanned antennas used in these radars are now being replaced with high-performance electronically-scanned phased-arrays. Phased-Array radars, however, require large number of active microwave components to scan electronically in both the azimuth and elevation planes, thus significantly increasing the cost of the entire radar system. To address this issue, CASA has designed a “Phase-Tilt” radar, that scans electronically in azimuth and mechanically in elevation. One of the core components of this system is the Phased-Array controller or the Array Formatter. The Array Formatter is a Field Programmable Gate Array (FPGA)-based master controller that translates user commands from a computer to control and timing signals for the radar system. The objective of this thesis is to design and test an FPGA-based Array Formatter for CASA’s Phase-Tilt radar system

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Color Segmentation on FPGA for Automatic Road Sign Recognition
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

In this master thesis work, a pipelined minimum distance classifier with reconfigurable structure on FPGA is presented. Its primary application is demonstrated on real-time color segmentation on hardware in a form of efficient feature classification using color components. This result is further extended by introducing a multi-class labeling module to label the segmented color components. The combination of these two modules can effectively detect road signs for an automatic road sign recognition system as a region of interest. To recognize the character of the road signs, the feature of histogram of orientation is also incorporated into this system and the minimum distance classifier is utilized for a second time in order to obtain the actual numbers shown on the road signs

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Measuring and Navigating the Gap Between FPGAs and ASICs
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

Field-programmable gate arrays (FPGAs) have enjoyed increasing use due to their low non-recurring engineering (NRE) costs and their straightforward implementation process. However, it is recognized that they have higher per unit costs, poorer performance and increased power consumption compared to custom alternatives, such as application-specific integrated circuits (ASICs). This thesis investigates the extent of this gap and it examines the trade-offs that can be made to narrow it. The gap between 90 nm FPGAs and ASICs was measured for many benchmark circuits. For circuits that only make use of general-purpose combinational logic and flip-flops, the FPGA-based implementation requires 35 times more area on average than an equivalent ASIC. Modern FPGAs also contain “hard” specific-purpose circuits such as multipliers and memories and these blocks are found to narrow the average gap to 18 for our benchmarks or, potentially, as low as 4.7 when the hard blocks are heavily used. The FPGA was found to be on average between 3.4 and 4.6 times slower than an ASIC and this gap was not influenced significantly by hard memories and multipliers. The dynamic power consumption is approximately 14 times greater on average on the FPGA than on the ASIC but hard blocks showed promise for reducing this gap. This is one of the most comprehensive analyses of the gap performed to date. The thesis then focuses on exploring the area and delay trade-offs possible through architecture, circuit structure and transistor sizing. These trade-offs can be used to selectively narrow the FPGA to ASIC gap but past explorations have been limited in their scope as transistor sizing was typically performed manually. To address this issue, an automated transistor sizing tool for FPGAs was developed. For a range of FPGA architectures, this tool can produce designs optimized for various design objectives and the quality of these designs is comparable to past manual designs. With this tool, the trade-off possibilities of varying both architecture and transistor-sizing were explored and it was found that there is a wide range of useful trade-offs between area and delay. This range of 2.1 × in delay and 2.0 × in area is larger than was observed in past pure architecture studies. It was found that lookup table (LUT) size was the most useful architectural parameter for enabling these trade-offs

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Characterization of FPGA-based High Performance Computers
نوع فایل: پایان نامه
سال انتشار: 2011

As CPU clock frequencies plateau and the doubling of CPU cores per processor exacerbate the memory wall, hybrid core computing, utilizing CPUs augmented with FPGAs and/or GPUs holds the promise of addressing high-performance computing demands, particularly with respect to performance, power and productivity. While traditional approaches to benchmark high-performance computers such as SPEC, took an architecture-based approach, they do not completely express the parallelism that exists in FPGA and GPU accelerators. This thesis follows an application-centric approach, by comparing the sustained performance of two key computational idioms, with respect to performance, power and productivity. Specifically, a complex, single precision, floating-point, 1D, Fast Fourier Transform (FFT) and a Molecular Dynamics modeling application, are implemented on state-of-the-art FPGA and GPU accelerators. As results show, FPGA floating-point FFT performance is highly sensitive to a mix of dedicated FPGA resources; DSP48E slices, block RAMs, and FPGA I/O banks in particular. Estimated results show that for the floating-point FFT benchmark on FPGAs, these resources are the performance limiting factor. Fixed-point FFTs are important in a lot of high performance embedded applications. For an integer-point FFT, FPGAs exploit a flexible data path width to trade-off circuit cost and speed of computation, improving performance and resource utilization. GPUs cannot fully take advantage of this, having a fixed data-width architecture. For the molecular dynamics application, FPGAs benefit from the flexibility in creating a custom, tightly-pipelined datapath, and a highly optimized memory subsystem of the accelerator. This can provide a 250-fold improvement over an optimized CPU implementation and 2-fold improvement over an optimized GPU implementation, along with massive power savings. Finally, to extract the maximum performance out of the FPGA, each implementation requires a balance between the formulation of the algorithm on the platform, the optimum use of available external memory bandwidth, and the availability of computational resources; at the expense of a greater programming effort

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Implementing Video Compression Algorithms on Reconfigurable Devices
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Methods for Securing the Integrity of FPGA Configurations
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

As Field Programmable Gate Arrays (FPGAs) continue to become integral parts of embedded systems, it is imperative to consider their security. While much of the research in this field is oriented toward the protection of the intellectual property contained in the FPGA’s configuration, the protection of the design’s integrity from malicious attack against the configuration is critical to the operation of the system. Methods for attacking the configuration are semi-invasive attacks, such as fault injection, and data tampering of incoming partial bitstreams. This thesis introduces methods for securing the integrity of an FPGA’s configuration. The design and implementation is discussed for a system that consists of three parts. The first subsystem monitors the running configuration. The second subsystem authenticates partial bistreams that may be used for repairing the configuration from malicious alterations during run-time. The third subsystem indicates if the system itself succumbs to a malicious attack. The system is implemented on-chip, allowing the FPGA to effectively secure itself from attack

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام : Cryptography and Cryptanalysis for Embedded Systems
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

A growing number of devices of daily use are equipped with computing capabilities. Today, already more than 98% of all manufactured microprocessors are employed in embedded applications, leaving less than 2% to traditional computers. Many of these embedded devices are enabled to communicate amongst each other and form networks. A side effect of the rising interconnectedness is a possible vulnerability of these embedded systems. Attacks that have formerly been restricted to PCs can suddenly be launched against cars, tickets, ID cards or even pacemakers. At the same time the security awareness of users and manufacturers of such systems is much lower than in classical PC environments. This renders security one key aspect of embedded systems design and for most pervasive computing applications. As embedded systems are usually deployed in large numbers, costs are a main concern of system developers. Hence embedded security solutions have to be cheap and efficient. Many security services such as digital signatures can only be realized by public key cryptography. Yet, public key schemes are in terms of computation orders of magnitude more expensive than private key cryptosystems. At the same time the prevailing schemes rely on very similar security assumptions. If one scheme gets broken, almost all cryptosystems employing asymmetric cryptography become useless. The first part of this work explores alternatives to the prevailing public key cryptosystems. Two alternative signature schemes and one public key encryption scheme from the family of post quantum cryptosystems are explored. Their security relies on different assumptions so that a break of one of the prevailing schemes does not affect the security of the studied alternatives. The main focus lies on the implementational aspects of these schemes for embedded systems. One actual outcome is that, contrary to common belief, the presented schemes provide similar and in some cases even better performance than the prevailing schemes. The presented solutions include a highly scalable software implementation of the Merkle signature scheme aimed at low-cost microprocessors. For signatures in hardware an FPGA framework for implementing a family of signature schemes based on multivariate quadratic equations is presented. Depending on the chosen scheme, multivariate quadratic signatures show better performance than elliptic curves in terms of area consumption and performance. The McEliece cryptosystem is an alternative public key encryption scheme which was believed to be infeasible on embedded platforms due to its large key size. This work shows that by applying certain implementational tricks both hardware and software implementation become feasible and show comparable performance to the prevailing schemes