مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Extending the Thread Programming Model Across CPU and FPGA Hybrid Architectures
نوع فایل: پایان نامه
سال انتشار: 2005
چکیده:

Field-programmable gate arrays (FPGA’s) have come a long way from the days when they served primarily as glue logic and prototyping devices. Today’s FPGA’s have matured to the level where they can host a significant number of programmable gates and CPU cores to create complete System on Chip (SoC) hybrid CPU+FPGA devices. These hybrid chips promise the potential of providing a unified platform for seamless implementation of hardware and software co-designed components. Realizing the potential of these new hybrid chips requires a new high-level programming model, with capabilities that support a far more integrated view of the CPU and the FPGA components than is achievable with current methods. Adopting a generalized programming model can lead to programming productivity improvement, while at the same time providing the benefit of customized hardware from within a familiar software programming. Achieving abstract programming capabilities across the FPGA/CPU boundary requires adaptation of a high-level programming model that abstracts the FPGA and CPU components, bus structure, memory, and low-level peripheral protocol into a transparent computational platform [2]. This thesis presents research on extending the multithreaded programming model across the CPU/FPGA boundary. Our objective was to create an environment to support concurrent executing hybrid threads distributed flexibly across CPU and FPGA assets. To support this generalized model across the FPGA, we have developed a Hardware Thread Interface (HWTI) that encapsulates mechanisms to support synchronization for FPGA based threads. The HWTI enables custom threads within the FPGA to be created, accessed, and synchronized with all other system threads through library API’s. Additionally, the HWTI is capable of managing “thread state”, accessing data across the system bus, and executing independently without the need to use CPU. Current multithreaded programming models use synchronization mechanisms such as semaphores to enforce mutual exclusion on shared resources. Semaphores depend on atomic operations provided through the CPU assembler instruction set. In multiprocessor systems, atomic operations are achieved by combinations of processor condition instructions integrated within memory coherency protocol of snooping data caches. Since these current mechanisms do not extend well to FPGA based threads, we have developed new semaphore mechanisms that are processor family independent. We achieve a much simpler solution and faster mechanisms (8 clock cycles or less) for achieving semaphore semantics with new atomic operations implemented within the FPGA. These new FPGA based semaphores provide synchronization for hardware, software and combinations of hardware/software threads. We also migrate sleep queues and wake-up capabilities that are normally associated with each semaphore into the FPGA. The wake up mechanism has the ability to deliver unblocked threads either to the CPU or FPGA. The queue and wake-up operation do not incur any system software overhead. As the total number of semaphore required in a system may be large, implementing separate queues for each semaphore can require significant FPGA resources. We address the resource utilization issue by creating a single controller and a global queue for all the semaphores without sacrificing performance. We solve the performance issue with hardware and queuing algorithm solutions. The semaphores are provided in the form of intellectual property (IP) cores. We have implemented recursive mutexes, recursive spin lock and condition variable cores in addition to the semaphore core. These cores provide synchronization services similar to the POSIX thread library. Toward the end of this thesis, we present an application study of our hybrid multithreaded model. We have implemented several image-processing functions in both hardware and software, but from within the common multithreaded programming model on a XILINX V2P7 FPGA. This example demonstrates hardware and software threads executing concurrently using standard multithreaded synchronization primitives transforming real-time images captured by a camera and displayed on a workstation

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

The rapid increase in the use of embedded systems for performing secure transactions, has proportionally increased the security threat, faced by such devices. Security threats are an issue of concern at both software and hardware level. The field of cryptography has been intensively researched for secure implementation techniques, methods to attack secure systems and countermeasures to avoid such attacks. In this thesis, we provide solutions for two interesting problems in the field of hardware security using reconfigurable hardware. First, we discuss a countermeasure to prevent side-channel analysis (SCA) attacks on an embedded system. We present an SCA-resistant processor design in the context of an embedded design flow for FPGA. It integrates an SCA-resistant custom instruction set on a soft-core CPU and derives an SCA resistance from dual-rail precharge principle. The resulting countermeasure applies to a broad class of block ciphers that consist of lookup tables and logical operations. While many countermeasures have been proposed previously, we show that our solution achieves an excellent trade-off between SCA resistance, (software and hardware) design complexity, performance, and circuit area cost. Secondly, we present a system to attack a special type of cryptography called Elliptic Curve Cryptography(ECC). It targets the Elliptic Curve Discrete Logarithmic Problem (ECDLP) for a NIST-standardized ECC-curve over 112-bit prime field. We implement a successful demonstration of an ECC cryptanalytic engine using the Pollard rho algorithm on a hardware-software co-integrated platform. We propose a novel, generalized architecture for polynomial-basis multiplication over prime field and its extension to a dedicated square module. Its design strategy is portable to other prime field moduli

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An FPGA Implementation of RM-BTC Codec Using Log-Map Algorithm
نوع فایل: پایان نامه
سال انتشار: 2002
چکیده:

Due to their powerful error correcting capability and superior coding gain, Turbo Codes are used in 3rd generation wireless and satellite communication systems. For these applications, efficient implementation of Turbo Codes, i.e., development of codec providing high throughput with small chip area and low power consumption is of growing importance. In this thesis, Turbo Code using Reed-Muller code as its constitute code is implemented in VHDL and logic synthesis is executed. The Max-Log-MAP algorithm is used due to its significantly reduced complexity and negligible performance degradation from MAP algorithm. The implementation of codec mainly focuses on achieving the smaller chip area and lower power dissipation, and target to device Virtex-E FPGA. For this purpose, the system and module level optimization of codec architecture is carefully considered through the parallelism and pipeline, interleaving technique, function unit sharing and memory access. The quantization and finite accuracy are also discussed. The simulation in RTL level on a wide variety of test vectors is done, and results show that the encoder/decoder execute properly and correct functionality is realized. The synthesis reports show that chip utilization is reasonable and more resource remains for future improvement

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of DPA-Resistant Circuit for FPGA
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the logic function of the copied submodule. Our technique has important applications in the design of side-channel resistant implementations in FPGA. Starting from an existing single-ended design, we are able to create a complementary circuit. The resulting overall circuit strongly reduces the power-consumption-dependent information leaks. We will show all the necessary steps needed to implement secure circuits on a FPGA, from initial design stage all the way to verification of the level of security through laboratory measurements. We show that the direct mapping of a secure ASIC circuit-style in an FPGA does not preserve the same level of security, unless our symmetrical routing technique is employed. We demonstrate our approach on an FPGA prototype of a cryptographic design, and show through power-measurements followed by side-channel power analysis that secure logic implemented with our approach is resistant whereas non-routing-aware directly mapped circuit can be successfully attacked

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: DCD Algorithm: Architectures, FPGA Implementations and Applications
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

In areas of signal processing and communications such as antenna array beam forming, adaptive filtering, multi-user and multiple-input multiple-output (MIMO) detection, channel estimation and equalization, echo and interference cancellation and others, solving linear systems of equations often provides an optimal performance. However, this is also a very complicated operation that designers try to avoid by proposing different sub-optimal solutions. The dichotomous coordinate descent (DCD) algorithm allows linear systems of equations to be solved with high computational efficiency. It is a multiplication-free and division-free technique and, therefore, it is well suited for hardware implementation. In this thesis, we present architectures and field-programmable gate array (FPGA) implementations of two variants of the DCD algorithm, known as the cyclic and leading DCD algorithms, for real-valued and complex-valued systems. For each of these techniques, we present architectures and implementations with different degree of parallelism. The proposed architectures allow a trade-off between FPGA resources and the computation time. The fixed-point implementations provide an accuracy performance which is very close to the performance of floating-point counterparts. We also show applications of the designs to complex division, antenna array beam forming and adaptive filtering. The DCD-based complex divider is based on the idea that the complex division can be viewed as a problem of finding the solution of a 2x2 real-valued system of linear equations, which is solved using the DCD algorithm. Therefore, the new divider uses no multiplication and division. Comparing with the classical complex divider, the DCD-based complex divider requires significantly smaller chip area A DCD-based minimum variance distortionless response (MVDR) beamformer employs the DCD algorithm for multiplication-free finding the antenna array weights. An FPGA implementation of the proposed DCD-MVDR beamformer requires a chip area much smaller and throughput much higher than that achieved with other implementations. The performance of the fixed-point implementation is very close to that of floating-point implementation of the MVDR beamformer using direct matrix inversion

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of the Onboard ADC and DAC on the Spartan 3E FPGA Platform
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

The objective of this project is to first interface the onboard ADC and DAC available in the Spartan 3E FPGA platform, so that the real signals too can be processed by the FPGA board. Thus first of all, the ADC was interfaced and the results were observed via ChipScope Pro. Then the DAC was interfaced and checked if it was working or not. Finally both were operated together, where registers were used to store the values of the digital data obtained from the ADC and then sent to the DAC for the reconstruction of the original signal, which could be observed via a DSO. ADC is a prime requirement whenever real-world signals come into play, hence interfacing the ADC is of great use and help in using the real-world signals for our use and further processing to extract vital information. DAC also aids in the said process similarly. The basic aim being that a given input signal should output exactly or nearly exactly the given input signal after having it passed through the ADC and the DAC

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: IP Camera on FPGA with a Web Server
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

As advances on fields such as embedded systems and networks emerge, new products with increasing features can be created. An example is an IP camera. An IP camera provides a good solution for remote real-time monitoring, allowing users to view and manage video and images with this new kind of networked devices. This thesis proposes a network IP camera solution based on the Altera Nios II embedded soft-core processor. The implementation consists on custom hardware and software so that the specific software runs on the developed hardware. The hardware design specifies all the modules implemented on a FPGA. Images captured by CMOS sensor are converted into RGB format and stored in the SDRAM. The NIOS II soft-core processor reads each frame, does the compression, and handles network connections. The software includes an operating system, μClinux, and a Web server running on top of it. Live images are compressed in Motion JPEG format by software, and the IP camera provides event management functionalities using additional implemented features. From the user point of view, the web user interface page allows live view from the camera and also system configuration, being compatible with the most popular browsers. It is available in Portuguese, English and German, with the possibility to add more languages

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: High Speed FPGA Implementation of Cryptographic Hash Function
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

In this thesis, a new method for implementing cryptographic hash functions is proposed. This method seeks to improve the speed of the hash function particularly when a large set of messages with similar blocks such as documents with common headers are to be hashed. The method utilizes the peculiar run-time reconfigurability feature of FPGA. Essentially, when a block of message that is commonly hashed is identified, the hash value is stored in memory so that in subsequent occurrences of the message block, the hash value does not need to be recomputed; rather it is simply retrieved from memory, thus giving a significant increase in speed. The system is self-learning and able to dynamically build on its knowledge of frequently occurring message blocks without intervention from the user. The specific hash function to which this technique was applied is Blake, one of the SHA-3 finalists

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Field Programmable Gate Arrays for Radar Front-End Digital Signal Processing
نوع فایل: پایان نامه
سال انتشار: 1999
چکیده:

As field programmable gate array (FPGA) technology has steadily improved, FPGAs have become viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPGA technology. As this thesis demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 7 MHz (with a clock rate of 117 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation and hardware implementation. Distributed arithmetic, bit-level systolic arrays, parallel multiplier/accumulator (MAC) cells, fast FIR algorithms, and frequency domain filtering were investigated to determine the most optimal structure for a FPGA FIR design, with distributed arithmetic resulting in the best performance. A custom VHDL cell-based layout tool was designed to improve the placement strategies of the Xilinx FPGA place and route tools, and improved the speed performance of the distributed arithmetic design by 37%

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of Genetic Algorithms in FPGA-based Reconfigurable Computing Systems
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

Genetic Algorithms (GAs) are used to solve many optimization problems in science and engineering. GA is a heuristics approach which relies largely on random numbers to determine the approximate solution of an optimization problem. We use the Mersenne Twister Algorithm (MTA) to generate a non-overlapping sequence of random numbers with a period of 219937-1. The random numbers are generated from a state vector that consists of 624 elements. Our work on state vector generation and the GA implementation targets the solution of a flow-line scheduling problem where the flowlines have jobs to process and the goal is to find a suitable completion time for all jobs using a GA. The state vector generation algorithm (MTA) performs poorly in traditional von Neumann architectures due to its poor temporal and spatial locality. Therefore its performance is limited by the speed at which we can access memory. With an approximate increase of processor performance by 60% per year and a drop of memory latency only 7% per year, a new approach is needed for performance improvement. On the other hand, the GA implementation in a general-purpose microprocessor, though performs reasonably well, has scope for performance gain in a parallel implementation. The parallel implementation of the GA can work as a kernel for applications that uses a GA to reach a solution. Our approach is to implement the state vector generation process and the GA in an FPGA-based Reconfigurable Computing (RC) system with the goal of improving the overall performance Application design for FPGA-based RC systems is not trivial and the performance improvement is not guaranteed. Designing for RC systems requires algorithmic parallelism in order to exploit the inherent parallelism of the FPGA. We are using a highlevel language that provides a level of abstraction from the lower-level hardware in the RC system making it difficult to fully exploit some of the architectural benefits of the FPGA. Considering these factors, we improve the state vector generation process algorithmically. Our implementation generates state vectors 5X faster than the previous implementation in an Intel Xeon microprocessor of 2GHz. The modified algorithm is also implemented in a Xilinx Virtex-4 FPGA that results in a 2.4X speedup. Improvement in this pre-processing step accelerates GA application performance as random numbers are generated from these state vectors for the genetic operators. We simulate the basic operations of a GA in an FPGA to study its behavior in a parallel environment and analyze the results. The initial FPGA implementation of the GA runs about 7X slower than its microprocessor counterpart. The reasons are explained along with suggestions for improvement and future work

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA Implementation of DHT Algorithms for Image Compression
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Digital image processing is the use of computer algorithms to perform image processing on digital images. The basic operation performed by a simple digital camera is, to convert the light energy to electrical energy, then the energy is converted to digital format and a compression algorithm is used to reduce memory requirement for storing the image. This compression algorithm is frequently called for capturing and storing the images. This leads us to develop an efficient compression algorithm which will give the same result as that of the existing algorithms with low power consumption. Compression is useful as it helps in reduction of the usage of expensive resources, such as memory (hard disks), or the transmission bandwidth required. But on the downside, compression techniques result in distortion (due to lossy compression schemes) and also additional computational resources are required for compression-decompression of the data. Reduction of these resources by comparing different algorithms for DHT is required. FPGA Implementations of different algorithms for 1-DHT using VHDL as the synthesis tool are carried out and their comparison gives the optimum technique for compression. Finally 2-D DHT is implemented using the optimum 1-D technique for 8x8 matrix input. The results obtained are discussed and improvements are suggested to further optimize the design

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a. The ADPLL model describes a novel method of implementation of CORDIC algorithm for the DDS system. This ADPLL model basically used for synchronization of closed loop RF control signals in a heavy ion particle accelerator can be implemented even in an ASIC which can be seen with a more general use for many a applications in the daily life

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Implementation of an FPGA-based Image Processing Framework for the EyeBot M6
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

The EyeBot M6 is the newest revision of an embedded system designated for the control of small mobile robots. Unlike previous revisions of the system, the EyeBot M6 features not only a 400MHz CPU running a fully fledged operating system but also a Xilinx FPGA accompanied by an SRAM and two cameras in a stereo setup. The recent advancements in FPGA fabrication not only induced lower prices but also permit the implementation of large signal processing algorithms in FPGAs. The current revision is the first EyeBot that tries to exploit the increasing capabilities of FPGAs for image processing purposes on small robots. This project focuses both on the low-level interfacing between the FPGA and the CPU and on the internal memory bus architecture required for image processing purposes. Previous work on the EyeBot M6 already showed that the communication between CPU and FPGA was unreliable. Sporadic transfer errors (mostly occurring during long DMA transfers, after FPGA design modifications or toolchain configuration changes) had a severe impact on reliability and maintainability of the system. In this thesis first of all an in-depth analysis of the previous system is undertaken and reveals several potential sources of error. The old system disregards the fact that CPU and FPGA are in distinct clock domains and therefore is prone to timing violations. Timing violations may occur in a register if one of its input signals changes too close to the clock edge that triggers the register. Because CPU and FPGA clocks are fully unrelated, a signal generated by the CPU may change close to an FPGA clock edge. In consequence this may induce a timing violation in a register inside the FPGA that samples this signal. The same scenario may happen in reverse, too. Timing violations may lead to a metastable state in the particular register. Because this results in unpredictable behavior of the register’s output the proper operation of all downstream units is compromised. In addition, it is found that an important step in the FPGA design flow has been omitted: Timing constraints are required to inform the development toolchain of the timing requirements caused by the components connected to the FPGA. If no constraints are applied to an FPGA design the toolchain will only implement the design according to its internal objectives. This might lead to an FPGA design that violates the timing requirements of the external components and thus to transfer errors, too. As a next step, possible solutions for the problem related to register timing violations are investigated. Several straightforward approaches (that would convert the design into a fully synchronous system) are found but can not be deployed on the EyeBot M6. The asynchronous interface therefore has to be utilized and used to interconnect CPU and FPGA in a safe manner. Because of its asynchronous nature timing violations cannot be fully avoided and their possible outcome therefore is evaluated. The probability of metastable events affecting the operation can be minimized using the gained knowledge on metastability. Based on these findings two interfacing approaches are identified and assessed. One interface supports arbitrary accesses to storage locations inside the FPGA but is unable to achieve the highest possible transfer rate on the bus between CPU and FPGA. The other interface, however, is capable of fully loading the bus but comes at the cost of setup-overhead. The former therefore is suitable for transmitting small amounts of data (e.g. for measurement or control purposes) and the latter is adequate for large, continuous transfers (e.g. images). The interfacing requirements are analyzed based on the expected data flow between CPU and FPGA. Based thereon, both interfaces are considered necessary and thus selected for implementation. The two interfaces are integrated into a bus bridge that terminates the asynchronous VLIO bus and instantiates a fully synchronous internal bus architecture. The operativeness of the bus bridge is verified both using simulation and testing on the actual hardware. Simulation alone is considered insufficient because the behaviour of a metastable register cannot be modelled. As a next step, timing constraints are applied to the new design. Regular synchronous constraints are used to specify the timing requirements of the CPU and the two cameras connected to the FPGA. In addition, several combinatorial constraints are applied to cover the asynchronous paths in the bus bridge. In a final step, a storage architecture required to access the external SRAM is designed. External storage is required by an image processing system that was developed simultaneously by a fellow student (see [29] for reference). The image processing system utilizes the stereo cameras of the EyeBot M6 and pursues the generation of a depth map. Its requirements are analyzed and the required high-level flow control is determined. Based thereon, the storage architecture is tailored to the estimated data flows generated by the image processing system. The existence of several clock domains in the system rules out a static, predefined arbitration scheme. Instead a simple priority-based arbitration is used to determine which flow is handled next by the storage system. Based on a performance estimation the achievable maximum frame rate of the complete system is given. However, it is found impossible to implement the proposed storage architecture with the current revision of the PCB. Due to a missing external clock feedback trace the clock skew between the FPGA and the external SRAM cannot be compensated. This rules out the application of timing constraints for the SRAM as well. Clock skew is a common problem in synchronous systems and Xilinx FPGAs contain dedicated resources capable of compensating it. A solution deploying two phase locked loops is found and the modifications required on the PCB are shown

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Evaluation of an FPGA and PCI Bus based Readout Buffer for the Atlas Experiment
نوع فایل: پایان نامه
سال انتشار: 2004
چکیده:

This dissertation evaluates a readout buffer system for the ATLAS detector trigger and data acquisition system. ATLAS is a high energy physics experiment at the large hadron collider (LHC) with the aim to reach new frontiers in the investigation of the structure of matter. The high precision ATLAS detector produces a huge amount of data, 40 TByte/s, which is reduced by a three-level trigger system for online event data selection. The readout buffer system acts as a data buffer while the second trigger level computes the trigger decision. ATLAS uses a sequential selection in the level 2 trigger which means that all event data required for the trigger decision is requested from the readout buffer component subsequently. This increases the complexity of the readout buffer device and its output event rate. Furthermore a region-of-interest (RoI) concept limits the amount of data necessary for the processing of one event inside the level 2 processor by defining the detector region with interesting data. Thus, approximately 10 kHz output rate have to be provided while feeding almost 1 kByte data packets with 100 kHz at the input. The evaluated implementation of this readout buffer should be based on commercial “oftheshelf” hardware. Thus a conventional Linux server PC with four PCI Bus segments has been used. This approach leads to uniformity in the ATLAS data acquisition system because all hardware beginning with the second trigger level is built of similar PCs. But a standard PC is not able to meet the previously mentioned requirements. Therefore it is extended (or accelerated) by a number of PCI based FPGA co-processor boards. Considering the above mentioned sequential selection and RoI concept, such a complex buffer component based on standard server PCs and FPGA co-processors has never been investigated before in high energy physics. The FPGA co-processor is a simple component extending the PC for the time critical receiving and buffering of data. It is able to process data from four ATLAS detector links which allows the grouping of 12 to 16 links in one PC. Measurements show that this system is able to sustain the ATLAS requirements. Currently Linux OS, running on the PC system and handling the Gigabit Ethernet network I/O with the rest of the data acquisition system, is the main bottleneck. Improving this could be the subject of future investigations

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Designing Biomedical Imaging Hardware Using Network on Chip NoC
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

The document describes the technique for implementing FFDs on NoC. The FFD technique uses B-spline algorithm for the modeling of 3-D deformable objects. Until now reconfigurable hardware like FPGA has not been applied widely to the area of image registration. Fixed-point implementation is required for effective implementation and high speed. The NoC described is lightweight circuit-switched architecture called PNoC. PNoC is a very flexible architecture that suits the FPGA-based systems. Our design description is captured in Verilog language and implemented on Xilinx XC2V6000 device at 37 MHz is parametrizable at the compile time and supports a range of the image resolutions and computational precisions