مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design Methodologies and Architectures for Digital Signal Processing on FPGAs
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

There has been a tremendous growth for the past few years in the field of embedded systems, especially in the consumer electronics segment. The increasing trend towards high performance and low power systems has forced researchers to come up with innovative design methodologies and architectures that can achieve these objectives and meet the stringent system requirements. Many of these systems perform some kind of streaming data processing that requires the extensive arithmetic calculations. FPGAs are being increasingly used for a variety of computationally intensive applications, especially in the realm of digital signal processing (DSP). Due to rapid increases in fabrication technology, the current generation of FPGAs contains a large number of configurable logic blocks (CLBs) and several other features such as on-chip memory, DSP blocks, clock synthesizers, etc. to support implementing a wide range of arithmetic applications. The high non-recurring engineering (NRE) costs and long development time for application specific integrated circuits (ASICs) make FPGAs attractive for application specific DSP solutions. Even though the current generation of FPGAs offers variety of resources such as logic blocks, embedded memories or DSP blocks, there is still limitation on the number of these resources being offered on each device. On the other hand, a mixed DSP/FPGA design flow introduces several challenges to the designers due to the integration of the design tools and complexity of the algorithms. Therefore, any attempt to simplify the design flow and optimize the processes for either area or performance is appreciated. This thesis develops innovative architectures and methodologies to exploit FPGA resources effectively. Specifically, it introduces an efficient method of implementing FIR filters on FPGAs that can be used as basic building blocks to make various types of DSP filters. Secondly, it introduces a novel implementation of correlation function (using embedded memory) that is vastly used in image processing applications. Furthermore, it introduces an optimal data placement algorithm for power consumption reduction on FPGA embedded memory blocks. These techniques are more efficient in terms of power consumption, performance and FPGA area and they are incorporated into a number of signal processing applications. A few real life case studies are also provided where the above techniques are applied and significant performance is achieved over software based algorithms. The results of such implementations are also compared with competing methods and trade-offs are discussed. Finally, the challenges and suggestions of integrating such methods of optimizations into FPGA design tools are discussed

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A Versatile DSP/ FPGA Structure
نوع فایل: پایان نامه
سال انتشار: 2001
چکیده:

This thesis is devoted to the development of a powerful digital computer equipped with flexible interfaces. It is designed to suit Rapid Prototyping and digital real-time simulation methods of power electronic and electrical drive (PE&ED) systems. This universal hardware basis unites the possibilities (benefit) to implement control equipment and complex but nevertheless low cost digital real-time simulators of PE&ED systems on the basis of a single basic hardware element. This aim is achieved by the synthesis of a new hardware structure based on the analysis of hardware requirements and a literature study yielding the proven elements. The new hardware structure is characterized by the use of powerful digital signal processors (DSPs) offering very high floating-point computing power and separate flexible control interfaces based on field-programmable gate arrays (FPGAs). This structure has been expanded to an over a large range scalable multiprocessor system taking into account the communication structure required by real-time simulators of PE&ED applications. A single board basic element is proposed as basis of a powerful and flexible, modular hardware structure. This element has been implemented in the form of the “ISEADSP board”. In addition, several FPGA based control interface designs are presented. Reference applications demonstrate the viability of the “ISEADSP board” implementation

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An FPGA-based 3D Graphics System
نوع فایل: پایان نامه
سال انتشار: 2005
چکیده:

This report documents the work done by the author to design and implement a 3D graphics system on an FPGA (Field Programmable Gate Array). After a preamble with a background presentation to the project, a very brief introduction in computer graphics techniques and computer graphics theory is given. Then, the hardware available to the project, along with an analysis of general requirements is examined. The following chapter contains the proposed graphics system design for FPGA implementation. A broad approach to separate the design and the eventual implementation was used. Two 3D pipelines are suggested - one fully capable high-end version and one which use minimal resources. The documentation of the effort to implement the minimal graphics system previously discussed then follows. The documentation outlines the work done without going too deep into detail, and is followed by the largest of the tests conducted. Finally, chapter seven concludes the project with the most important project conclusions and some suggestions for future work

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: CAD Techniques for Robust FPGA Design Under Variability
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

The imperfections in the semiconductor fabrication process and uncertainty in operating environment of VLSI circuits have emerged as critical challenges for the semiconductor industry. These are generally termed as process and environment variations, which lead
to uncertainty in performance and unreliable operation of the circuits. These problems have been further aggravated in scaled nanometer technologies due to increased process variations and reduced operating voltage. Several techniques have been proposed recently for designing digital VLSI circuits under variability. However, most of them have targeted ASICs and custom designs. The flexibility of reconfiguration and unknown end application in FPGAs make design under variability different for FPGAs compared to ASICs and custom designs, and the techniques proposed for ASICs and custom designs cannot be directly applied to FPGAs. Very few techniques have been proposed for FPGA design under variability, with varying degrees of improvement in timing/power variability. However, these have not dealt with leveraging CAD, architecture and circuits co-design methodologies for FPGA design under variability, and further, have not accounted for the impact of the variability in V_dd arising due to IR drops which is important because the performance of a circuit becomes more sensitive to process parameters as V_dd is reduced. An important design consideration is to minimize the modifications in architecture and circuit to reduce the cost of changing the existing FPGA architecture and circuit. The work in this thesis develops CAD and architecture/circuit design techniques for FPGAs to improve the timing and power yield of FPGA designs under process variations. In the case of environment variations this work focuses on developing design techniques for reducing IR-drops. The focus of this work can be divided into three principal categories, which are, improving timing yield under process variations, improving power yield under process variations and improving the voltage profile in the FPGA power grid. The work on timing yield improvement implements a Statistical Static Timing Analysis (SSTA) framework to analyze the circuit delay under process variations, such that the statistical distribution of the critical delay can be computed. In this work, the structure of the interconnect is analyzed and it is shown that an optimum number of buffers can be inserted in the interconnect to reduce the variation in circuit delay. Several interconnect architectures are analyzed, under the constraints of the FPGA structure, to find the best architecture which leads to smallest (µ + 3σ) of the critical delay. The placement and routing tools are then enhanced such that the delay variability is accounted for when optimizing the critical delay of the circuit. Results indicate that up to 28% improvement in (µ + 3σ) of the critical delay can be obtained from the proposed methodology. The work on power yield improvement for FPGAs selects a low power dual-V_dd FPGA design as the baseline FPGA architecture for developing power yield enhancement techniques. A low power FPGA architecture is selected because, before applying power yield enhancement techniques to a design, it is necessary that a low power design technique is implemented. The power yield enhancement technique proposed in this work is essentially a CAD technique for placement and dual-V_dd assignment. The proposed CAD techniques reduce the correlation between leaking FPGA elements such that the total variability of leakage is reduced and power yield is improved. Results indicate that an average reduction of 15% in leakage variability can be obtained from the proposed methodology, with an average of 7.8% power yield improvement. A mathematical programming technique is also proposed to determine the parameters of the buffers in the interconnect such as the sizes of the transistors and threshold voltage of the transistors, all within constraints, such that the leakage variability is minimized under delay constraints. Results show a reduction of 26% in leakage variability without any delay penalty. The variability in supply voltage in the power grid occurs due to currents being drawn by the underlying devices. The IR-drops in the power grid leads to reduced speed of the circuit and may also affect the functionality of the design. To reduce IR-drops in the power grid of FPGAs two CAD techniques are proposed in this work. The first technique is an IR-drop aware place and route technique which reduces the high currents drawn in local regions of the chip to reduce the IR-drops. The placement and routing routines are enhanced to incorporate the information about the current distribution profile in the power grid. This is done by redistributing the blocks and nets in such a way so that the spatial distribution of the switching activity profile is more smooth. The CAD techniques result in maximum IR-drop reduction of up to 53% and a reduction in standard deviation of spatial supply voltage distribution by up to 66%. The second technique is also a CAD technique applied at the clustering stage, where the LUTs are clustered into fixed size logic blocks. The idea here again is to reduce the currents being drawn in a local region. This is achieved by carefully selecting the LUTs to be added to form a cluster. This is because if a cluster has many LUTs with high switching activity nets, then that cluster will experience a large IR-drop. The clustering technique is enhanced such that the new IR-drop aware clustering technique takes into account the switching activities of the nets in the current cluster and the switching activities of the nets connected to potential LUTs that can be added to the current cluster. Results indicate that up to 36% reduction in maximum IR-drop and 27% reduction in standard deviation of the spatial distribution of V_dd can be achieved from the proposed techniques

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Neural Network-based Face Detector Implementation on a VIRTEX2 Pro FPGA Platform
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

Face detection is a vital part towards face recognition and is a vital task in security and intelligent vision-based human computer interaction applications. Current software face detection implementations lack the computational ability to support detection in real time video streams. Hence the need for hardware implementations of face detection systems arises. Hardware implementations are not only desirable because of their speed that allows for real time video processing, but also because hardware implementations can be optimized to have the best possible results in terms of area and power consumption. This thesis focuses on the design of a hardware system on an FPGA platform for the purpose of performing upright frontal view face detection on an image frame. The proposed design consists of a neural network that performs face detection on a 320x240 input frame. The neural network receives a 20x20 search window from the image and classifies the window as a face or no face. The system output is an image where the windows that were classified as faces are marked. An important part of this thesis is the effective allocation of the FPGAs resources in order to design a system capable of parallel processing of frames. The weights and thresholds for the neural network were provided in collaboration with Video mining incorporated. The weights and thresholds are for up frontal viewing and for a specific data set. The neural network training was done offline and the detection is done online. The implemented face detection system can process approximately 30 frames per second whereas software implementations process between 15-22 frames per second under favorable conditions. The detection frame rate also indicates that the system can perform face detection in real time video streams

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Acceleration of Face Detection Algorithm on an FPGA
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

This thesis presents hardware architecture for face detection acceleration system based on AdaBoost algorithm using Haar features which is widely known as Viola and Jones algorithm. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing as well as classifier, and parallel processing multiple classifiers to accelerate the processing speed of the face detection system. Also we will introduce a control module to reduce the overall system latency by discarding of non-face sub-frame before going under integral image generation. The proposed architecture for face detection has been designed using Verilog HDL and targeted by Stratix IV GX FPGA of Altera series. Its performance has been measured and compared with equivalent software and one concurrent hardware implementations as well. We show about 3 and 36 times increase of system performance for 640*480 size image over the equivalent software and hardware implementation, respectively. In addition, these results for image of size 320*240 rose up to 3 and 150 times comparing to the same implementations. Another acceleration approach is examined by increasing the shift step of scanning sub-frame. The result was successful most of the time

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design of Efficient FPGA Circuits for Matching Complex Patterns in Network Intrusion Detection Systems
نوع فایل: پایان نامه
سال انتشار: 2003
چکیده:

The objective of this research is to design and develop a reconfigurable string matching co-processor using field-programmable gate array (FPGA) technology that is capable of matching thousands of complex patterns at gigabit network rates for network intrusion detection systems (NIDS). The motivation for this work is to eliminate the most significant bottleneck in current NIDS software, which is the pattern matching process. The tasks involved with this research include designing efficient, high-performance hardware circuits for pattern matching and integrating the pattern matching co-processor with other NIDS components running on a network processor. The products of this work include a system to translate standard intrusion detection patterns to FPGA pattern matching circuits that support all the functionality required by modern NIDS. The system generates circuits efficient enough to enable the entire ruleset of a popular NIDS containing over 1,500 patterns and 17,000 characters to fit into a single low-end FPGA chip and process data at an input rate of over 800 Mb/s. The capacity and throughput both scale linearly, so larger and faster FPGA devices can be used to further increase performance. The FPGA co-processor allows the task of pattern matching to be completely offloaded from a NIDS, significantly improving the overall performance of the system

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Reconfigurable Platform-Based Design in FPGAs for Video Image Processing
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

This thesis examines methods for increasing productivity in the design of reconfigurable systems. Unrelenting advances in the transistor density of integrated circuits have resulted in Field-Programmable Gate Arrays (FPGAs) with sufficient resources to contain complete digital systems. The complexity of system-level design for these increasingly heterogeneous devices is compounded when reconfigurability is included. Platform-based design is a methodology which manages complexity by imposing constraints on the system architecture to facilitate a high degree of design reuse. It is the argument of this thesis that given an appropriate adaptation of platform-based design to FPGAs, not only is design productivity increased, but reconfigurability can be exploited by construction of systems at run-time. This is given the nomenclature late integration. A modular system architecture is developed, which is suitable as a template for a single-FPGA platform supporting late integration. The architecture is an evolution of an existing multiple-FPGA board-level system, and targets the video image processing application domain. Assembling a system at run-time requires components of the system to communicate reliably post-assembly. A rigorous analysis of the communication between modules across shared media is presented. This demonstrates that the application of appropriate constraints enables communication to be resolved analytically. Finally, the system assembly process takes place within the FPGA, using a technique of dynamic reconfiguration. New tools and design processes have been created for implementing dynamic reconfiguration in real, state of the art FPGAs

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Advanced Audio Coding on an FPGA
نوع فایل: پایان نامه
سال انتشار: 2002
چکیده:

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA-based Data Acquisition System for Ultrasound Tomography
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

Ultrasound Tomography involves the acquisition and analysis of large amounts of data, both of which must be done at high speed in order to be implemented in a mobile product. FPGA technology promises to provide the necessary parallel processing capabilities in order to accomplish various strenuous processing procedures. At the same time the technology allows a system to be designed and prototyped quickly and cost-effectively. However, an FPGA device is limited by the speed at which it can acquire raw data. To facilitate ultrasound tomography, the external circuitry is responsible for acquiring high resolution data at high speeds that are sufficient in order to allow effective signal processing. The circuitry must also perform the opposite function, that being the ability to transform high resolution digital data into analogue signals at high speed. This thesis sets out to investigate the recent developments in FPGA technology, looking specifically at the benefits that FPGAs deliver to embedded system design. It then moves on to suggest a software/hardware configuration that will provide a cheap, fast-tracked working demonstration of an ultrasound tomography system. It takes the reader through the process of building the entire system

designing and implementing the external hardware
creating a customized soft-core Nios II processor
interfacing all the system components
writing the control code
testing the system
demonstrating valid results

Lastly, and most importantly, since this project merely lays the foundation for further exploring FPGA technology, a range of possible project extensions are suggested

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Development of an FPGA-based Distributed Computing Processing Platform
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using a distributed system of field-programmable gate array (FPGA) boards. The software framework provides users with the ability to easily develop applications that exploit the processing power of FPGAs while the hardware core manager framework gives users the ability to configure and interact with multiple FPGA boards and/or hardware cores. This thesis describes the design and development of these frameworks and analyzes the performance of a system that was constructed using the frameworks. The performance analysis included measuring the effect of incorporating additional hardware components into the system and comparing the system to a software-only implementation. This work draws conclusions based on the provided results of the performance analysis and offers suggestions for future work

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Interfacing a Processor Core in FPGA to an Audio System
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

The thesis project consists on developing an interface for a Nios II processor integrated in a board of Altera (UP3- 2C35F672C6 Cyclone II). The main goal is show how the Nios II processor can interact with the other components of the board. The Quartus II software has been used to create to vhdl code of the interfaces, compile it and download it into the board. The Nios II IDE tool is used to build the C/C++ files and download them into the processor. It has been prepared an application for the audio codec integrated in the board (Wolfson WM8731 24-bit sigma-delta audio CODEC). The line input of the audio codec receives an analog signal from a laptop, this signal is managed by the control interface of the audio codec. The converters ADCs and DACs are stereo 24-bit sigma delta and they are used with oversampling digital interpolation and decimation filters. The digital interface of the audio codec sends the digital signal to the Nios II processor and receives the data from the processor. After building the interfaces for the audio codec and the processor, it has been prepared an application in C++ language for the processor that modifies the volume of the signal. The signal come back to the audio codec and it is possible to check the results with headphones or speakers at the line output of the audio codec

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

In this thesis, a both method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance. Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of Image Processing Algorithms on FPGA Hardware
نوع فایل: پایان نامه
سال انتشار: 2000
چکیده:

Recently, Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of algorithms suited to video image processing applications. The unique architecture of the FPGA has allowed the technology to be used in many such applications encompassing all aspects of video image processing. The goal of this thesis is to develop FPGA realizations of three such algorithms on two FPGA architectures. As image sizes and bit depths grow larger, software has become less useful in the video processing realm. Real-time systems such as those that are the target of this project are required for the high speeds needed in processing video. In addition, a common problem is dealing with the large amount of data captured using satellites and ground-based detection systems. DSP systems are being employed to selectively reduce the amount of data to process, ensuring that only relevant data is passed on to a human analyst. Eventually, it is expected that most video processing can and will take place in DSP systems, with little human interaction. This is obviously advantageous, since human data analysts are expensive and perhaps not entirely accurate

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Implementation of an FPGA-based Image Processor
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

This thesis explores using a hybrid processing approach for doing application specific memory intensive processing. The hybrid system uses a general purpose processor (GPP) in conjunction with an FPGA-based Image Processor (FIMP) to improve performance for image processing applications. The hybrid architecture is designed to implement an image registration algorithm that partitions the algorithm into separate functions executing either on the GPP or the FIMP system. This thesis explores the trade-offs of different configurations for FIMP architecture, utilizing the flexibility of reconfigurable hardware to achieve maximum performance. The FIMP system was designed in Verilog HDL and implemented on the Xtremedata XD1000 system, which uses an Opteron main processor and an Altera Stratix II FPGA co-processor. Multi-core systems of up to 32 nodes were implemented, using three network topologies: a bus, a ring and a fully connected mesh. Benchmark results for the FIMP system are compared to software execution. For an image registration algorithm using 256x256 gray scale images use of a 16 node fully connected FIMP system as a co-processor produced a 1.65 times speedup over the GPP alone