مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: The Current State of FPGA Technology in the Nuclear Domain
نوع فایل: Technical Report
سال انتشار: 2012
چکیده:

Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Design of an FPGA-based Lithium-Ion Battery Charger System
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

Nowadays, the number of portable electronics products such as mobile telephones and laptop computers has grown explosively. These developments have resulted in massive demand for secondary batteries. The advantages of lithium-ion batteries include no memory effect, high operation voltage, and high energy density. Therefore, it is the most popular secondary battery for consumer electronics. In this paper, a FPGA (Field Programmable Gate Array)-based lithium-ion battery charger system is developed. The concerned charger system consists of an FPGA-based controller, a data acquisition system and a programmable power source. The proposed system can achieve the goals such as digital programmability, userfriendly interface, data monitoring ability and stable voltage/current source. According to the experimental results, the proposed charger system is capable of charging the lithiumion batteries with less than 1.5 % current ripple

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: An FPGA-based Smart Database Storage Engine
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

Ever increasing database sizes and query complexity presents an opportunity for hybrid, FPGA-based co-processor systems to significantly improve database performance. Although performance opportunities for FPGAs in fast data processing field are wellknown, the design of a FPGA-based hybrid system still need for compromise between system exibility and high FPGA-compilation cost. Elimination of this compilation cost would dramatically increase the efficiency of FPGA-based hybrid systems. In this thesis, we implement an FPGA-based database storage engine that achieves this goal. Our FPGA-based database storage engine is able to accept dynamic selection and projection based filtering queries at runtime without extra FPGA-compilation cost. This is accomplished through two parts. First, we introduce a FPGA-readable data storage format, which allows FPGAs to recognize and project data on-the-fly. Second, we design a selection evaluation module based on the selection truth table, which gives our storage engine the capability of evaluating dynamic Boolean expressions at wire speed. Furthermore, we explore the FPGA-DB server interface, which is accomplished through implementing a data communication framework based on PCI Express. Finally, we show that the performance is able to gain through our FPGA-based co-processing database storage engine

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: FPGA Implementation of Circular Spatial Filter under High Noise Variance Conditions
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

The noise in digital images is additive in nature in various cases. Such kind of noise is called to as Additive White Gaussian Noise (AWGN). This noise gets into image while transmission, reception, storage and retrieval It is difficult to suppress AWGN because it corrupts more or less all the pixels in a image. Some filters such mean filter had been proposed to suppress AWGN but in most cases it incorparates a blurring effect in the image. Image denoising is usually done before display or further processing like feature extraction, segmentation, object identification, texture analysis, etc. The intention of denoising is to suppress the noise efficiently and retaining the edges and other necessary features as far as possible. Many efficient digital image filters are found that perform well under low noise conditions. But in the cases of moderate and high noise conditions their performance is limited. Thus, it is felt that there is sufficient scope to investigate and develop quite efficient. And proposed a spatial filter named as circular spatial filter which performs well under high noise conditions. Suppose CSF has to be used for real time applications such as before displaying the video on HDTV a real time application. It is hard to implement this algorithm on a general purpose computer where high amount of concurrency is needed. So we have chosen FPGA as a target which is suitable for video and image processing. Here we chose virtex-5 Xilinx board to implement the algorithm. The performance of the designed filters is compared with the existing filters and the MATLAB simulation [1] in terms of peak-signal-to noise ratio, root-mean-squared error

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Design and FPGA Implementation of CORDIC-based 8-point 1D DCT Processor
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

CORDIC or CO-ordinate Rotation DIgital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique [7] which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. Using a prescribed sequence of conditional additions or subtractions the CORDIC arithmetic unit can be controlled to solve either of the following equations

Y’= K (Ycos λ+ Xsin λ); k is a constant
X’= K (Xcos λ - Ysin λ); K is a constant

In this project
A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 10.1. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by ChipScopePro analysis of the output logic waveforms was performed

Using this CORDIC core a DCT processor was designed to calculate the 8-point 1D DCT. The functionality and operational correctness of this processor was tested, first on the test-bench and then via ChipScopePro analysis, post FPGA implementation

The output obtained in both the cases was compared with the actual values to test for consistency and the percentage of accuracy was established. Power consumption and FPGA resource utilization were observed. The results obtained were discussed

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: FPGA Implementation of Low-Complexity ICA-based Blind Multiple-Input Multiple-Output OFDM Receivers
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

In this thesis Independent Component Analysis (ICA) based methods are used for blind detection in MIMO systems. ICA relies on higher order statistics (HOS) to recover the transmitted streams from the received mixture. Blind separation of the mixture is achieved based on the assumption of mutual statistical independence of the source streams. The use of HOS makes ICA methods less sensitive to Gaussian noise. ICA increase the spectral efficiency compared to conventional systems, without any training/pilot data required. ICA is usually used for blind source separation (BSS) from their mixtures by measuring non-Gaussianity using Kurtosis. Many scientific problems require FP arithmetic with high precision in their calculations. Moreover a large dynamic range of numbers is necessary for signal processing. FP arithmetic has the ability to automatically scale numbers and allows numbers to be represented in a wider range than fixed-point arithmetic. Nevertheless, FP algorithm is difficult to implement on the FPGA, because the algorithm is so complex that the area (logic elements) of FPGA leads to excessive consumption when implemented. A simplified 32-bit FP implementation includes adder, Subtractor, multiplier, divider, and square rooter The FPGA design is based on a hierarchical concept, and the experimental results of the design are presented

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Intelligent IP Camera: An FPGA Motion Detection Implementation
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

This Report deals with an intelligent camera implementation. This camera is linked with a Altera Field Programmable Gate Array (FPGA) platform on a DE2 Board where a motion detection algorithm is implemented. The main goal of this project is to analyze the feasibility of optimizing video surveillance with an FPGA. The aim is therefore to create a prototype to do several function, with some requirements. A room is monitored and the video captured by the camera sensor is displayed on a VGA screen. The video is recorded only when motions are detected. Then, the video is stored on a SD-Card and accessible on an Ethernet network. Hardware and software co-design is studied to implement the motion detection algorithm on a Nios II softcore processor, with hardware acceleration. The project is composed of background analysis which details the main context of the project and details the problem to be answered in this report. Then, a design model study is proposed to enhance the analysis, design and implementation of the project. The system analysis and design and the motion detection algorithm analysis and design are successively given. Finally, the implementation of the proposed solution and the testing and experiments parts are detailed. The video capture and transmission are successfully implemented. Those parts are implemented in full hardware, using Verilog programming language. The motion detection algorithm implemented is a background subtraction algorithm. As the recording and storage blocks are not successfully implemented, frames stored on the desktop file system are used to test the algorithm. It is fully implemented in software, using ANSI-C programming language. Storage and recording parts are not implemented due to memory chip problems. As a conclusion, the optimization of video surveillance by using FPGA seems to be possible, but with a custom and optimized platform instead of a *standard one* (i.e. produced by a manufacturer). In facts, the memory chip of the selected board is an 8 MB SDRAM chip, while for this project two 256 MB SDRAM would have been better

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Interfacing a Processor in FPGA to an Audio System
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

The thesis project consists on developing an interface for a Nios II processor integrated in a board of Altera (UP3- 2C35F672C6 Cyclone II). The main goal is show how the Nios II processor can interact with the other components of the board. The Quartus II software has been used to create to vhdl code of the interfaces, compile it and download it into the board. The Nios II IDE tool is used to build the C/C++ files and download them into the processor. It has been prepared an application for the audio codec integrated in the board (Wolfson WM8731 24-bit sigma-delta audio CODEC). The line input of the audio codec receives an analog signal from a laptop, this signal is managed by the control interface of the audio codec. The converters ADCs and DACs are stereo 24-bit sigma delta and they are used with oversampling digital interpolation and decimation filters. The digital interface of the audio codec sends the digital signal to the Nios II processor and receives the data from the processor. After building the interfaces for the audio codec and the processor, it has been prepared an application in C++ language for the processor that modifies the volume of the signal. The signal come back to the audio codec and it is possible to check the results with headphones or speakers at the line output of the audio codec

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: A Memory Controller for FPGA Applications
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

As designers and researchers strive to achieve higher performance, field-programmable gate arrays (FPGAs) become an increasingly attractive solution. As coprocessors, FPGAs can provide application specific acceleration that cannot be matched by modern processors. Most of these applications will make use of large data sets, so achieving acceleration will require a capable interface to this data. The research in this thesis describes the design of a memory controller that is both efficient and flexible for FPGA applications requiring floating point operations. In particular, the benefits of certain design choices are explored, including: scalability, memory caching, and configurable precision. Results are given to prove the controller's effectiveness and to compare various design trade-offs

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Landmine Detection Architecture and their Implementation on FPGA
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

The data collected by the NIITEK GPR, high range resolution (HRR) ground-penetrating radar (GPR), results in a digitized raw video representing signals reflected at the surface of as well as internal to the landmine due to changes in impedances, materials dielectric properties. This digitized signal has to undergo several stages of preprocessing in order to produce a binary-valued- sequence. A part of this sequence contains a specific length of string that is a characteristic of a mine pattern. The mine pattern, to be recognized from a longer string of processed GPR data, has to be presented to a landmine detector. The landmine detector not only detects the mine but also classifies them and discriminates the mines from clutter (noise). Three pattern recognizers, one reset Finite State Machine (FSM) and two behaviorally equivalent Parallel Correlators are designed to detect multiple landmines simultaneously. Alternative implementations of these processing modules are compared with respect to chip area in terms of number of slices (real-estate or chip area) and speed (processing time), as a function of the number of landmines to be simultaneously recognized. It is found that the reset FSM is smallest in size of all the architectures but the slowest, whereas, the first Parallel Correlator is largest in size and the second Correlator, the fastest. An alternative pattern recognizer, a non-reset Finite State Machine, sometimes known as a Rabin-Scott Machine, is also analyzed in terms of chip area (slices) and speed(processing time) but with respect to the relevant parameter, the maximum number of states in FSM. It was apparent that both- the size as well as the speed of the FSM increases with the increase in the number of states

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: A Dynamically Reconfigurable FPGA-based Content Addressable Memory for IP Characterization
نوع فایل: پایان نامه
سال انتشار: 2000
چکیده:

IP characterization is the process of classifying IP packets into groups depending on information in the header. In this report three implementations of FPGA-based dynamically reconfigurable Content Addressable Memories (CAMs) are described for Internet Protocol Version 6 characterization. These CAMs are characterized by a large width of the search word, a relatively small number of CAM words and the fact that these may contain ‘’don’t cares’’. To implement the CAMs, the CAM words were divided into a number of reconfigurable match blocks. In the first CAM implementation called the fixed length CAM, the number of these blocks is equal for all words. A more advanced architecture was developed as well, where blocks that merely store ‘don’t cares’ are omitted which leads to a varying number of reconfigurable blocks for each word. By placing these blocks in a smart way, more CAM words can be stored. This CAM is referred to as variable length CAM. In the last implementation an explicit priority mechanism was added where the priority can be programmed for each CAM word. This eliminates the slow insertion and deletion times without adding significant additional hardware costs. The CAMs were implemented on a Xilinx Virtex FPGA and the reconfiguration of the this device is done dynamically from a Java environment. A user interface for changing the contents of the CAM was developed, together with a hardware interface to let the software communicate with the FPGA. It has been shown that using this technology, a CAM containing over 100 words of 320 bits can be implemented, that is able to perform more than 7 million look ups per second

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Video over IP: An Example Reconfigurable Computing Application
نوع فایل: پایان نامه
سال انتشار: 2003
چکیده:

As the demand for live video communication increases, the devices available to the users need to be made faster, smaller, lower power, and easily modifiable. This project demonstrates an example video over IP application using a Compaq IPaq along with a field programmable gate array used for data processing. The video data is passed directly from the camera to the network card via the gate array, thus avoiding unnecessary delay and computation requirements imposed on the CPU by regular video over IP communication software. The application achieves a display rate of 9 frames per second with 76800 byte frames, corresponding to a wireless throughput of 5.5Mbps. The CPU usage is reduced to 1/3 of that used by a standard video over IP implementation operating at the same rate

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: An FPGA Implementation of a Digital FM Modulator
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

The increase in speed and density of programmable logic devices such as Field Programmable Gate Arrays (FPGA) enables ever more complex designs to be constructed within a short time frame. The flexibility of a programmable device eases the integration of a design with a wide variety of components on a single chip. Since Frequency Modulation (FM) is an analog modulation scheme, performing it in the digital domain introduces new challenges. The details of these challenges and how to deal with them are also explained. This thesis presents the design of a digital stereo FM modulator including necessary signal processing, such as filtering, waveform generation, stereo multiplexing etc. The solution is comprised of code written in Very high speed integrated circuit Hardware Description Language (VHDL) and a selection of free Intellectual Property (IP)-blocks and is intended for implementation on a Xilinx FPGA. The focus of the thesis lies on area efficiency and a number of suggestions are given to maximize the number of channels that can be modulated using a single FPGA chip. An estimation of how many channels that can be modulated using the provided FPGA, Xilinx XC6SXL100T, is also presented

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Design and FPGA Implementation of an Adaptive Demodulator
نوع فایل: پایان نامه
سال انتشار: 1997
چکیده:

Signal Processing systems for communications will have to operate in rapidly changing environments. To suitably adapt to the varying requirements, control strategies targeted at selecting and tuning the signal processing algorithms need to be developed. The work being reported in this thesis is part of the bigger initiative by DARPA to develop and exploit reconfigurable computing for evolving defense systems. This work focuses on the use of automatic recognition of modulation type of the input signal to suitably reprogram the FPGA as a particular demodulator. The modulation schemes considered are PSK2 PSK4 and FSK2. This is used as a case study to demonstrate how reconfigurable computing can be a promising choice for building more adaptable and robust signal processing and communication systems. This thesis first surveys the existing algorithms of Automatic Modulation Recognition (AMR). These algorithms are briefly analyzed to consider the feasibility of implementing them in hardware. A novel algorithm of automatic modulation is proposed and its FPGA implementation discussed in detail. It is also discussed how the run-time reconfigurability offered by the FPGA can aid in building a universal demodulator. The complete design flow followed for synthesizing the designs for FPGAs is presented. Design and implementation details of the individual demodulators is discussed in great detail. Certain hardware optimizations that exploit the available FPGA architectures are documented. The test setup used for testing these radios is briefed. Finally all the demodulators and the modulation recognizer are integrated into a run-time reconfigurable set up. Results from testing are reported and discussed

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: An FPGA Implementation of a Modulator for Digital Terrestrial Television According to the DTMB Standard
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of exisiting channels is increased with new methods of error correction coding and modulation. This thesis presents the design and implementation of a modulator for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in VHDL and is intended for implementation on an FPGA