مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Reconfigurable FPGA Accelerator for Databases
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

Database management systems have traditionally been implemented entirely in software. However, adding hardware to database cluster servers to gain more speed has its price. Firstly, the cost of the hardware itself, secondly the increased power consumption from the numerous processors that have to be used. The purpose of this study is to investigate how partial run-time reconfiguration in FPGAs can be used to accelerate databases. It aims to show how an FPGA based query processor can work in collaboration with a regular software database to accelerate certain queries. This thesis proposes a novel way of using dynamic partial reconfiguration in FPGAs to process arbitrary queries in hardware. We investigate how SQL queries can be decomposed and turned into hardware modules that are 'stitched' together at run-time to form a stream processing data-path. Consequently, a set of customizable hardware modules that each can implement a range of SQL operators are presented. In addition, the thesis gives a method for floorplanning a high capacity FPGA for slot based partial reconfiguration. In the end, by the help of a case study we can conclude that the main bottleneck is the interface to the host computer. Another interesting finding is that unlike conventional databases, the accelerator is not slowed down by a more complex query. On the contrary, filtering out results actually speeds it up

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An FPGA-Based Real-Time Simulator for the Analysis of Electromagnetic Transients in Electrical Power Systems
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

A physical control/protection platform needs to be tested and its functionality verified prior to installation and commissioning. Closed-loop testing of a physical control/protection platform, in a real-time simulator environment is practically the only option to safely and thoroughly verify the design integrity and evaluate its functionality and performance. Moreover, a real-time simulator is also required to conduct statistical switching studies, as it substantially reduces the total run time of the study. This thesis proposes and develops a generalized methodology for implementation of the power system equations in the FPGA environment. The developed methodology enables real-time operation, for closed-loop testing of physical control/protection platforms in hardware-in-the-loop (HIL) configuration, and even faster-than-real-time operation, for statistical switching studies. Based on the developed methodology, an FPGA-based simulator is developed and tested. The salient features of the proposed implementation are

It enables the use of a nanosecond range simulation time-step to simulate large systems in real-time, in contrast to the ¹s range time-steps used in the existing simulators. Thus it is also able to provide a wide frequency bandwidth for the simulation results

It retains the calculation time, within each simulation time-step, nearly fixed irrespective of the size of the system

It eliminates the need for the corrective measures, adopted in the existing real-time simulators, to reduce error due to the lack of synchronization between the simulation time-grid and the output signals of the control/protection platform under test

As an integral part of this work, this thesis proposes and develops the modified two-layer network equivalent (M-TLNE). The salient feature of the M-TLNE is its computational efficiency, as compared to the existing network equivalents, which makes it a prime choice for statistical switching studies and real-time simulation of electromagnetic transients. This thesis also proposes a generalized methodology, applicable to both single and multi-port network equivalents for both single- and multi-phase systems, for developing the proposed M-TLNE. The developed methodology ensures the stability and passivity of the M-TLNE

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design Principles for the Development of Space Technology Maturation Laboratories Aboard the International Space Station
نوع فایل: پایان نامه
سال انتشار: 2005
چکیده:

This thesis formulates seven design principles for the development of laboratories which utilize the International Space Station (ISS) to demonstrate the maturation of space technologies. The principles are derived from the lessons learned from more than two decades of space technology research at the MIT Space Systems Laboratory and the existence of unique resources aboard the ISS. The thesis provides scientists with a design framework for new laboratories and an evaluation framework to responds to a call by the National Research Council to institutionalize science activities aboard the ISS. Experience from previous missions and research on the resources available at the ISS led to the development of the SPHERES Laboratory for Distributed Satellite Systems (DSS), which constitutes the experimental part of the thesis. SPHERES allows tests in a representative, risk-tolerant environment aboard the ISS to demonstrate metrology, control, and autonomy algorithms for DSS. The implementation of ground-based and ISS-based facilities permits incremental technology maturation by enabling iterative research; algorithms can mature through multiple research cycles with increasing complexity. The SPHERES Guest Scientist Program supports research by multiple scientists: since the Spring of 2000 SPHERES has enabled research on formation flight, communications requirements, mass properties identification, autonomous rendezvous and docking, and tethered formation flight. The design principles were formulated by first identifying the features of the SPHERES laboratory which allow it to fulfill the MIT SSL Laboratory Design Philosophy and utilize the ISS correctly, and then finding the applicability of these features to space technology maturation research. The seven principles are: Principle of Iterative Research, Principle of Enabling a Field of Study, Principle of Optimized Utilization, Principle of Focused Modularity, Principle of Remote Operations and Usability, Principle of Incremental Technology Maturation, and Principle of Requirements Balance. The design framework is used to assess SPHERES and suggest a new design iteration which better satisfies the design principles. The evaluation of SPHERES concludes that it is ready for operations aboard the ISS, since the modular design of SPHERES allows most of the proposed design changes to occur after the initial deployment.

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: CoRAM: An In-Fabric Memory Architecture for FPGA-Based Computing
نوع فایل: پایان نامه
سال انتشار: 2011
دانـلـود
چکیده:

Field Programmable Gate Arrays (FPGA) have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despite their newfound potency in both processing performance and energy efficiency, FPGAs have not gained widespread acceptance as mainstream computing devices. A fundamental obstacle to FPGA-based computing can be traced to the FPGA’s lack of a common, scalable memory abstraction. When developing for FPGAs, application writers are often responsible for crafting the application-specific infrastructure logic that transports the data to and from the processing kernels, which are the ultimate producers and consumers within the fabric. Very often, this infrastructure logic not only increases design time and effort but will inflexibly lock a design to a particular FPGA product line, hindering scalability and portability. To create a common, scalable memory abstraction, this thesis proposes a new FPGA memory architecture called Connected RAM (CoRAM) to serve as a portable bridge between the distributed computation kernels and the edge memory interfaces. In addition to improving performance and efficiency, the CoRAM architecture provides a virtualized memory environment as seen by the hardware kernels to simplify application development and to improve an application’s scalability and portability

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Development of Digital Circuits on a Virtual Sblock FPGA
نوع فایل: پایان نامه
سال انتشار: 2004
دانـلـود
چکیده:

The research field of Evolvable Hardware (EHW) may be said to be able to evolve structurally complex circuits. However, functionally complex circuits are still beyond what can realistically be evolved. The problem of evolving large complex circuits is connected to the lack of scalability in evolutionary algorithms. Inspired by how nature solves the scalability problem, developing a complex individual from a relatively simple description, a developmental approach to evolution of large complex circuits is addressed herein. The fact that there are few or no commercially available evolution and development friendly devices provides a challenge to this research field. As such, an architecture including evolution and development friendly features was designed. The architecture is a virtual FPGA –device independent but may be mapped to any FPGA device. As such, a hardware realization of evolving solutions is possible i.e. intrinsic evolution. The architecture is based on relatively simple building blocks –Sblocks with only local communication. The architecture results in reduced configuration data and an architecture that guarantees for non-destructive configurations. As an experimental platform for development of circuits, a development process is integrated on-chip offering a platform for development and evaluation of circuite solutions on-chip. The evolution and development friendly platform is implemented on a Virtex 1000E FPGA. Applying development mapping to circuit design requires a development mapping capable of using the compact information provided in the genotype to develop circuit structures with given functional properties. As a first case study, the principles of L-Systems [26] was tuned to the development of circuit structures. The development process is rule based i.e. the genotype is composed of a set of rules. The L-System based development process was also extended to include local knowledge and defined cell types i.e. basic building blocks. Incorporation of such knowledge opened for development of structural properties such as repeated and symmetrical circuit structures. To open for functionality, a circuit topology with functional properties needed to be addressed. To free the interpreting of the functionality for a circuit from the strict structural properties of conventional circuits i.e. placement of input, output ports and interconnect between gates, a non-uniform 2D cellular automata is chosen. As a development mapping is not necessarily a mapping to a final circuit with a given functionality but rather a mapping to an emerging circuit with emerging functionality identification of emerging functionality was investigated

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Evolution on FPGAs for Feature Extraction
نوع فایل: پایان نامه
سال انتشار: 2001
دانـلـود
چکیده:

Evolvable hardware circuits are presented for solving pattern recognition problems in image data sets, especially for feature extraction in remotely sensed multi-spectral imagery. The circuits are targeted at Field Programmable Gate Arrays (FPGAs). FPGAs are digital circuits that can be configured to meet application specific computational needs by downloading a configuration bit-string. Evolutionary Algorithms are optimization techniques that are unique in their simplicity and therefore their flexibility. This flexibility has led to a hardware design methodology known as Evolvable Hardware, which uses Evolutionary Algorithms to explore novel hardware solutions. FPGAs are ideal targets for Evolvable Hardware because the programming bit-string is a good match to the genetic bit-string used in Evolutionary Algorithms. However, experience has shown that evolving hardware solutions using the raw configuration bit-string is often impractical due to the large design space that must be explored. Evolvable FPGA circuits are described where the design space is severely constrained to an interconnected array of meaningful high-level operators. First, novel variants of Cellular Automata are evolved on FPGAs to solve binary pattern recognition problems. These experiments constrain the FPGA bit-string to a meaningful network of Cellular Automata building blocks. This means problem specific constraints can be more easily implemented, which leads to a smaller, more relevant design spaces. The search space is then further constrained to enable the Cellular Automata architecture to be applied to gray-value image processing, This leads to a class of non-linear filter known as Stack Filters. Stack filters are found to have several properties desirable to FPGA implementation, but lack sufficient computational power to solve practical gray value texture classification problems. Second, evolvable network architectures are implemented on FPGAs to solve practical feature extraction problems that are found in multi-spectral images. These experiments constrain the FPGA bit-string to a pipelined array of high-level nodes. The computational power of the Stack Filter is enhanced by considering the set of Generalized Stack Filters, which leads to the class of Morphological Networks. A Morphological Network node is approximately one quarter the size of a Neural Networks node when implemented on FPGAs. However, the Neural Network has superior performance on multi-spectral feature extraction problems in experiment. Both networks perform poorly on broad area features that include many spectral signatures. Third, a novel network node is proposed that addresses this problem by exploiting both spectral and spatial information. The node includes both Morphological and Neural Network functionality. By using high-level network building blocks, the design space is directed towards solutions that are particularly useful for the feature extraction problem. This includes a rich design space of linear and non-linear filters from traditional image processing algorithms. Finally, the node is used to build multi-layered networks and is applied to a variety of multi-spectral feature extraction problems. An advanced evolutionary algorithm is used to optimize the network. Once trained, the network can be applied to large image data sets with over two orders of magnitude speed-up compared to software implementations. Promising results are found in comparing the evolvable network architecture with advanced spatio-spectral software solutions and more traditional techniques. Results also indicate there is room for future research, and the directions considered most fruitful are described

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An FPGA Based Power Electronic System for Automotive Applications
نوع فایل: پایان نامه
سال انتشار: 2010
دانـلـود
چکیده:

Piezoelectric materials are used to convert electrical energy to mechanical energy and vice-versa. The precise motion that results when an electric potential is applied to a piezoelectric material is fundamental for nano positioning. Actuators using the piezo effect have been commercially available for 35 years and in that time have transformed the world of precision positioning and motion control. Piezoelectric actuators can perform sub-nanometer moves at high frequencies because they derive their motion from solid state crystalline effects. One of the main features is no rotating or sliding parts to cause friction so no maintenance is required and they are not subject to wear. Moreover piezo actuators can move high loads with virtually no power in static operation because present capacitive loads. These actuators can be used for various kinds of application [18]. They are employed for micro and nano positioning tasks as well as in hydraulic and pneumatic valves, where they replace magnetic control element. As mentioned before, from the electrical point of view the equivalent model of a piezoelectric actuator can be represented at low frequencies as a non linear capacitance with hysteresis. This capacitance depends on the area and thickness of the ceramic, as well as on its material properties, and considering stack actuators, which are assembled with thin, laminar wafers of electro active ceramic material electrically connected in parallel, it also depends on the number of layers

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Real-time FPGA Radiometric Calibration of an Imaging Fourier Transform Spectrometer
نوع فایل: پایان نامه
سال انتشار: 2009
دانـلـود
چکیده:

Despite all their advantages, Fourier Transform Spectrometers (FTSs) present a specific drawback compared to other spectrometer technologies. As their name implies, a Fourier transform must be performed on the raw data in order to obtain a spectrum. For single-pixel instruments, this is not a problem thanks to the Fast Fourier Transform (FFT) algorithm and modern computers. However, for Imaging FTSs (IFTSs) with large Focal-Plane Arrays (FPAs) (i.e. 320x256 pixels), the amount of data to be processed can rapidly become overwhelming for most modern computers, especially if the goal is to process it in real time. A Field Programmable Gate Array (FPGA) System-on-a-Chip (SoC)! architecture is presented which can perform real-time data processing of IFTS data. Datacube co-adding, FFTs, spectral cropping and radiometric calibration can be performed at data rates in excess of 34 Megapoints per second (Mpts/s). The calculations done on the FPGA are not as precise as those done on a PC with 64-bit floating-point numbers. However, the errors introduced by using fixed-point numbers on the FPGA do not degrade the noise of the Long Wave (LW) IFTSs by more than 10 %

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Integrated, FPGA Based NMR Teslameter and Power Supply for Accelerator Magnets
نوع فایل: پایان نامه
سال انتشار: 2007
دانـلـود
چکیده:

Particle accelerators today have numerous magnets that require controlling. These include magnets for analysing, beam-path selection, focusing, etc. Also, design specifications are becoming tighter. A typical modern magnet power supply is expected to have a resolution of 16-bit and a stability of 10 ppm. This thesis addresses two research areas. First, various aspects of high-performance accelerator magnet power supplies are investigated. An isolated dual-stage 3.5 kW converter is designed. The concept is verified through practical measurements. The control system and high-resolution pulse-width modulation are implemented within a field-programmable gate array. Second, a nuclear-magnetic resonance probe is designed and simulated. It is intended to provide a measurement of field-strength for feed-back purposes. Some adjustments are made with existing technology in order to decrease the time between successive measurements to the order of 10 μs. Also, the support systems (central processing unit, hardware drivers, etc.) are designed, implemented in the field-programmable gate array and tested successfully

[38404357]

پاسخ : پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design for Embedded Image Processing on FPGAs
نوع فایل: E_Book
سال انتشار: 2011

با سلام.
من این کتاب رو حدود 10 روز هست دارم میخونم.به نظرم میتونست یکم ساده تر بیان کنه.
ازدوستان کسی کتاب دیگه ای دراین زمینه سراغ نداره؟
ممنون

[حمید نجفی]

پاسخ : پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

با سلام.
من این کتاب رو حدود 10 روز هست دارم میخونم.به نظرم میتونست یکم ساده تر بیان کنه.
ازدوستان کسی کتاب دیگه ای دراین زمینه سراغ نداره؟
ممنون

لطفا اینجا پست غیر از مقاله نزارین
ممنونم

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A Neural Network Face Detector Design Using Bit-width Reduced FPU On FPGA
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

This thesis implemented a field programmable gate array (FPGA)-based face detector using a neural network (NN), as well as a bit-width reduced floating-point unit (FPU). An NN was used to easily separate face data and non-face data in the face detector. The NN performs time consuming repetitive calculation. This time consuming problem was solved by a Field Programmable Gate Array (FPGA) device and a bit-width reduced FPU in this thesis. A floating-point bit-width reduction provided a significant saving of hardware resources, such as area and power. The analytical error model, using the maximum relative representation error (MRRE) and the average relative representation error (ARRE), was developed to obtain the maximum and average output errors for the bit-width reduced FPUs. After the development of the analytical error model, the bit-width reduced FPUs and an NN were designed using MATLAB and VHDL. Finally, the analytical (MATLAB) results, along with the experimental (VHDL) results, were compared. The analytical results and the experimental results showed conformity of shape. It was also found that while maintaining 94.1% detection accuracy, a reduction in bit-width from 32 bits to 16 bits reduced the size of memory and arithmetic units by 50%, and the total power consumption by 14.7%

[ya_montazar]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook ها&#1740

[ebook]
The Designer's Guide to VHDL
Peter J.Ashenden-Jim Lewis
Third-edition
2008
http://mim-shin-shahid.persiangig.co...L.pdf/download

[ya_montazar]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

[ebook]
Circuit Design and Simulation with VHDL

Veloni Pedroni
2nd Edition
2010
http://mim-shin-shahid.persiangig.co...9.pdf/download

[ya_montazar]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

IEEE Standard VHDL Language Reference Manual (IEEE Std 1076™-2008)
2009
http://mim-shin-shahid.persiangig.co...8.pdf/download
(لازم به توجهه که این استاندارد تا این تاریخ در ISE پشتیبانی نمیشود.استاندارد ISE همون ۹۳ هست)