مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A High-Speed Timing-Aware Router for FPGAs
نوع فایل: پایان نامه
سال انتشار: 1998
چکیده:

Digital circuits can be realized almost instantly using Field-Programmable Gate Arrays (FPGAs), but unfortunately the CAD tools used to generate FPGA programming bit-streams often require several hours to compile large circuits. We contend that there exists a subset of designers who are willing to pay for much faster compile times by having to use more resources on a given FPGA, a larger FPGA, or some decrease in the circuit speed. A significant portion of the compile time tends to be spent in the placement and routing phases of the compile. This thesis focuses on the routing phase and proposes a new high-speed timing-aware routing algorithm. The execution speed of the new router is very fast when the FPGA contains at least 10% more routing resources than the minimum required by a circuit. For example, when targeting a model of the Xilinx 4000XL FPGA, the routing time for a 250,000 gate circuit is 127 seconds on a 300 MHz UltraSPARC. The circuit delay is only 19% higher compared to a high-quality timing-driven router. Since some routing problems are inherently difficult and will unavoidably take a long time to route, the practical use of high-speed routing requires that the tool must be able to predict if the routing task is: (i) difficult and will take a long time to complete, or (ii) impossible to complete. In this research, we present a method for making these predictions and show that it is accurate

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Circuit Partitioning for Application-Dependent FPGA Testing
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

Application-dependent FPGA testing is performed to ensure that a particular user-defined application is implemented on fault-free areas of an FPGA. Applying this type of test technique leads to yield increases and cost reductions in the use of FPGAs. In this thesis, we propose a novel application-dependent FPGA testing strategy, in which a recursive circuit partitioning algorithm is employed to obtain a testing configuration solution for a user-specific application. This algorithm is implemented and the experimental results are analyzed to demonstrate the effectiveness of the proposed testing strategy. Our experimental results show that the circuit partitioning method can be used to provide a reasonable solution for an arbitrary application with significantly improved fault coverage and an approximately minimized number of cut points

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of a FPGA-based Interface to a High Speed Image Sensor
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

This thesis is part of a project in which a high speed camera is developed. Subject of this work is the interconnection of an image sensor LUPA-3000 and a FPGA. The FPGA is connected to the multi channel Low-Voltage Differential Signaling (LVDS) data interface and handles the calibration of the individual channels. The LVDS receiver interface can handle asynchronous data signals and synchronizes them for subsequent processing. This complex LVDS receiver design is discussed and its functionality explained in detail. For testing, a VHDL design was developed including an asynchronous LVDS transmitter that transfers data to the receiver component through wires which interconnect the FPGA IOs. After simulating the entire design it was tested in practice on a FPGA evaluation board. This communication system was verified utilizing a ChipScope logic analyzer. The interface design which is connected to the image sensor includes the receiver component as well as an unit that provides an easy to use configuration interface for programming the image sensor. Besides, the exposure control is realized within the VHDL design. To evaluate the hardware design, that is connected to the image sensor, a SystemC testbench was developed, that includes a software model of the LUPA-3000 image sensor to verify the functionality of the overall design

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Evaluation of a Parameterizable NoC Router for FPGAs

نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

The Network-on-Chip (NoC) approach for designing (System-on-Chip) SoCs is currently emerging as an advanced concept for overcoming the scalability and efficiency problems of traditional on-chip interconnection schemes. This thesis addresses the design and evaluation of a parameterizable NoC router for FPGAs. The importance of low area overhead for NoC components is crucial in FPGAs, which have fixed logic and routing resources. We achieve a low area router design through optimizations in switching fabric and dual purpose buffer/connection signals. We propose a component library to increase re-use and allow tailoring of parameters for application specific NoCs of various sizes. A set of experiments were conducted to explore the design space of the proposed NoC router using different values of key router parameters: channel width (flit size), arbitration scheme and IP-core-to-router mapping strategy. Area and latency results from the experiments are presented and analyzed

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Embedded Systems and FPGAs for Implementation of Control Oriented Models -- Applied to Combustion Engines
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

Performance demands put on combustion engines are ever increasing, e.g. demands on emissions and fuel consumption. The increased demands together with new combustion concepts increase the need for feedback engine and combustion control. Mathematical models are considered important in order to implement high performance feedback control, as well as to perform diagnostic functions in vehicles. Various implementation platforms which can be used to implement mathematical models in vehicles are described in this thesis; embedded processors, FPGAs and ASICs. Which of these implementation platforms to choose must be decided based on the intended application and current demands on performance. Embedded systems, ASICs and FPGAs are discussed based on literature found in the field, covering a wide span of considerations. Furthermore a number of considerations which are important when implementing algorithms and logic in embedded processors and FPGAs are described. The theory is put into practice in the thesis, implementing a heat release calculation on an FPGA and developing and implementing a NOx model in an embedded processor. To be able to implement a fast NOx model several techniques were used. Parts of the model were tabulated, difficult operators such as division were avoided and the properties of fast C code was kept in mind. This thesis combines the areas of automatic control, electronic hardware design and development of embedded software, and applies it to combustion engine control. The work undertaken indicate different possibilities when implementing high speed control oriented models in FPGAs and embedded processors. This thesis aims to fill a gap between state space models, common in automatic control, and high fidelity physical models, commonly used for simulation, by providing a method to develop high fidelity control oriented models which are low in computation demand and implementable in FPGAs and embedded processors

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Smart Detector - An Intelligent Hardware-based Video Surveillance
نوع فایل: پایان نامه
سال انشار: 2004
چکیده:

Digital image processing (DIP) has a number of industrial applications like video surveillance and target recognition. Such applications are coupled with a number of problems: motion detection, tracking, and activity interpretation. The most fundamental of these three, motion detection has been the focus of this thesis with its implementation on a reconfigurable computer based on Field Programmable Gate Arrays (FPGA ‘s). Motion detection algorithms are mostly implemented in software, which make them less attractive for real-time purposes like the target of this project; video surveillance. Inspired by Grimson et al and Haritaoglu et al methods of image segmentation, a unique image segmentaion algorithm has been developed and used in this project, which requires no floating-point or transcendental operations and hence can be implemented in both hardware and software with ease. Our results show a significant performance over the two base algorithms as well as an increased processing time on a highly pipelined architecture, like FPGA. The execution time is enhanced by several orders of magnitude (10 to 100 times) when compared to a highly optimised software version

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Security Properties of a Class of True Random Number Generators in Programmable Logic
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Nowadays, digital equipment such as computers with Internet and cellular phones are commonly used for communication. The users want secure communications, meaning that confidentiality, integrity and authenticity are maintained throughout the session. Confidentiality means that only the intended recipient has access to the transmitted information, integrity ensures that the information is protected against modifications, and finally, authenticity guarantees the identities of the communicating parties. All these security aspects can be achieved using cryptographic techniques and protocols. In a cryptographic system where the algorithm is public, the entire security depends on the used cryptographic key. These keys are generated by using pseudo random number generators (PRNGs) using an algorithm combined with a seed or true random number generators (TRNGs) based on a physical property generating random noise. A TRNG is preferred if the cryptographic system requires a high level of security. Traditionally, a cryptographic system is implemented in an application specific integrated circuit (ASIC), but during the recent years a field programmable gate array (FPGA) has become an attractive alternative. The advantages of using an FPGA compared to an ASIC are the flexibility regarding update of the configuration for correcting errors or adding new functionality, an easier and faster development process and availability of FPGA devices on short notice from the vendors. On the other hand, the flexibility of an FPGA with the possibility of changing the configuration makes it more vulnerable against attacks. The challenge is to design a TRNG in an FPGA with good statistical properties, a reasonable high bit rate and robustness against attacks. In this thesis, a practical and functional enhancement of a class of TRNGs based on several equal length oscillator rings is proposed. The generation of true randomness is based on the uncertainty of where in time a transition, i.e. a change from logical zero to logical one or vice versa, of the oscillator ring outputs occur due to the presence of jitter. The enhanced TRNG was implemented in several FPGA families and the security properties were examined. The statistical properties were investigated by running the statistical test suites NIST SP 800-22 and DIEHARD, and the test results showed that this TRNG passes these tests. Due to the proposed enhancement the number of oscillator rings could be reduced and a post-processor was not needed in order to pass the statistical tests. Restart experiments from an identical reset state showed that this TRNG generates true randomness and not only pseudo randomness. A detailed spectral analysis was performed on each of the building blocks of this TRNG by investigating the frequency spectrum both in theory and by simulations showing that it approaches the frequency spectrum of an ideal random number generator. The purpose was also to optimize the design parameters in order to achieve a high bit rate. Experiments were performed and a bit rate of 300Mbit/s was achieved while generating random bits with good statistical properties. Even though the statistical properties were found to be good, understanding the noise source and quantifying the amount of entropy are important in the evaluation of an TRNG. A model based on the accumulation of jitter was proposed and simulations were carried out showing the influence of the different design parameters and technology properties on the number of hits close to a transition region defined by the standard deviation of the accumulated jitter. The simulations show that the proposed TRNG with high probability generates bits with high entropy at every sampling point. An investigation of the properties of oscillator rings implemented in three different FPGAs was performed in order to examine the interaction between rings located close to each other, the correlation and dependency between the rings and also the dispersion of the oscillator ring frequencies. The investigation revealed that there is interaction between some of the rings and a few of them could be regarded as correlated due to almost identical ring frequencies. The experiments showed that there are differences between the examined SRAM based FPGAs compared to a flash FPGA regarding the dispersion of the ring frequencies. The robustness of the TRNG was examined by employing an attack by superimposing a noise signal onto the power supply voltage to the FPGA. Four different TRNG designs were investigated and the two designs based on several oscillator rings were not influenced by this attack while two other reference TRNG designs were. Simulations were performed in order to explain the observed behavior on the TRNGs consisting of oscillator rings. A more exact power model of a microcontroller bus based on the influence of crosstalk due to capacitive couplings between the bus lines was proposed in order to more precisely determine the energy consumption. This model could for instance be used in a side-channel attack determining the encryption key with reduced computational effort. A TRNG based on the proposed design was implemented in a real life cryptographic system with good results showing that this TRNG is both practical and secure. In addition, this TRNG design is easy to implement in programmable logic, the placement of the inverters inside the FPGA is not critical, it is robust against temperature and power supply variations and not influenced by effects related to aging. All this makes a TRNG based on XOR of several sampled oscillator rings a suitable component in a cryptographic system

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: On pin-to-wire routing in FPGAs
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

While FPGA interconnect networks were originally designed to connect logic block output pins to input pins, FPGA users and architects sometimes become motivated to create connections between pins and specific wires in the interconnect. These pin-to-wire connections are motivated by both a desire to employ routing-by-abutment, in modular, pre-laid out systems, and to make direct use of resources in the fabric itself. The goal of this work is to measure the difficulty of forming such pin-to-wire connections. We show that compared to a at placement of the complete system, the routed wire-length and critical path delay increase by 6% and 15% respectively, and the router effort increases 3.5 times. We show that while pin-to-wire connections impose increased stress on the router, they can be used under some circumstances. We also measure the impact of increasing routing architecture flexibility on these results, and propose a low-cost enhancement to improve pin-to-wire routing

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Security for volatile FPGAs
نوع فایل: Technical report
سال انتشار: 2009
چکیده:

With reconfigurable devices fast becoming complete systems in their own right, interest in their security properties has increased. While research on \FPGA security" has been active since the early 2000s, few have treated the field as a whole, or framed its challenges in the context of the unique FPGA usage model and application space. This dissertation sets out to examine the role of FPGAs within a security system and how solutions to security challenges can be provided. I offer the following contributions. I motivate authenticating configurations as an additional capability to FPGA configuration logic, and then describe a flexible security protocol for remote reconfiguration of FPGA-based systems over insecure networks. Non-volatile memory devices are used for persistent storage when required, and complement the lack of features in some FPGAs with tamper proofing in order to maintain specified security properties. A unique advantage of the protocol is that it can be implemented on some existing FPGAs (i.e., it does not require FPGA vendors to add functionality to their devices). Also proposed is a solution to the “IP distribution problem" where designs from multiple sources are integrated into a single bitstream, yet must maintain their confidentiality. I discuss the difficulty of reproducing and comparing FPGA implementation results reported in the academic literature. Concentrating on cryptographic implementations, problems are demonstrated through designing three architecture-optimized variants of the AES block cipher and analyzing the results to show that single figures of merit, namely “throughput" or “throughput per slice", are often meaningless without the context of an application. To set a precedent for reproducibility in our field, the HDL source code, simulation testbenches and compilation instructions are made publicly available for scrutiny and reuse. Finally, I examine payment systems as ubiquitous embedded devices, and evaluate their security vulnerabilities as they interact in a multi-chip environment. Using FPGAs as an adversarial tool, a man-in-the-middle attack against these devices is demonstrated. An FPGA-based defense is also demonstrated: the first secure wired “distance bounding" protocol implementation. This is then put in the context of securing reconfigurable systems

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Reliability-Aware Placement and Routing for FPGAs
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Soft errors are intermittent malfunctions of hardware that are not reproducible. They may affect the data integrity and affect the system operation. These errors are growing reliability threat in VLSI system design. A soft error occurring in a memory cell or register is called a Single Event Upset (SEU). Designs mapped into Field Programmable Gate Arrays (FGPAs) are more vulnerable to soft errors than ASIC implementations, due to the large number of configuration memory used to map the design into the FPGA. An SEU causes a unique failure mode in the mapped design due to the unique architecture of FPGAs. In this work, we try to mitigate the effects of SEUs in SRAM based FPGAs. An SEU occurring in one of the configuration bits of the FPGA may cause a permanent error in the implemented circuit. Since the majority of FPGA real estate is dedicated for SRAM configuration bit, mitigating soft error in these configuration bits can improve the reliability of the mapped design. The goal of this work is the development of an SEUaware placement and routing tool that is capable of producing an implementation that is less vulnerable to SEUs. To achieve this, we modified the cost function for the placement and the routing part of the VPR tool to reduce the effects of SEU in the final mapped design. The VPR tool is a general purpose FPGA placement and routing tool that is widely accepted and used in the academic field. Two classes of errors that can be caused by an SEU in the routing resources were considered: switch open errors and switch short errors. During placement, we applied a cost function to estimate for the sensitivity to reduce the chances of the occurrence of these errors. We optimize for the switch open errors by minimizing the number of switches used for routing a net of the circuit. For reducing switch short errors, we try to minimize the overlapping area between nets. During routing, we carefully assign routing resources for the nets to minimize these errors. By using this approach we were able to reduce the number of total sensitive errors by 58% in average, but that reduction comes at the cost of increased critical path delay by on 54% on average

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Power Supply Solutions for Modern FPGAs
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signal processing, medical imaging, and high-performance computing. This thesis outlines the issues related to powering FPGAs. Supplying and conditioning power are the most fundamental functions of an electrical system. A loading application, be it an FPGA, cannot sustain itself without energy, and cannot fully perform its functions without a stable supply. The fact is transformers, generators, batteries, and other offline supplies incur substantial voltage and current variations across time and over a wide range of operating conditions. They are normally noisy and jittery not only because of their inherent nature but also because high power switching circuits like central processing units (CPUs) and digital signal processing (DSP) circuits usually load it. These rapidly changing loads cause transient excursions in the supposedly noise free supply, the end results of which are undesired voltage droops and frequency spurs where only a dc component should exist. The main component of a power supply is a voltage regulator. The role of the voltage regulator is to convert these unpredictable and noisy supplies to stable, constant, accurate, and load independent voltages, attenuating these ill fated fluctuations to lower and more acceptable levels. Linear or switching regulators based power supplies will be proposed and simulated. Today’s FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power-on, and soft start requirements can result in unreliable power-up or potential damage to FPGAs

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Improved Framework for fast and Efficient Memory-Based Frame Data Reconfiguration for Multi-Row Spanning Designs on FPGAs
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Reconfigurable computing is an evolving paradigm in computer architecture where the ability to load different designs onto a field programmable gate array (FPGA) at execution time has proven useful in adapting FPGA prototypes to a wide range of applications. Reconfiguration techniques can be primarily categorized as Partial Dynamic Reconfiguration (PDR) and Partial Bitstream Relocation (PBR). PDR involves reconfiguring a single Partial Reconfiguration Region (PRR) with a partial bitstream, while PBR is targeted at reconfiguring multiple PRRs on the FPGA with a partial bitstream. Previous techniques have primarily focused on using either slower on-chip memory or on-chip memory-based solutions to store the partial bitstream, and then reconfigure a PRR on the FPGA. Another technique called Accelerated Relocation Circuit (ARC) provides a more efficient method where a PRR (active bitstream) is used to relocate to other PRRs on the y using minimal on-chip memory. This thesis proposes a novel technique for Memory-based Frame Data Reconfiguration (M-FDR) of multi-row PRRs. ARC hardware was re-architected to provide an improved frame data reconfiguration framework, called Accelerated Memory-based Reconfiguration Circuit (AMRC) for use in MBR scenarios. A performance prediction model is also proposed that confirms the speedup achieved by AMRC, in comparison to ARC and earlier methods. This technique was found to be 26.6% faster than ARC in PRR-PRR relocation. In comparison to other relocation techniques like Bit Relocation Filter (BiRF), AMRC provides a speedup of 231x. The AMRC method was also able to dynamically parallelize multi-row designs with an average context switching time of 0.37 ms

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Evaluation of a Parameterizable NoC Router for FPGAs
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

The Network-on-Chip (NoC) approach for designing (System-on-Chip) SoCs is currently emerging as an advanced concept for overcoming the scalability and efficiency problems of traditional on-chip interconnection schemes. This thesis addresses the design and evaluation of a parameterizable NoC router for FPGAs. The importance of low area overhead for NoC components is crucial in FPGAs, which have fixed logic and routing resources. We achieve a low area router design through optimizations in switching fabric and dual purpose buffer/connection signals. We propose a component library to increase re-use and allow tailoring of parameters for application specific NoCs of various sizes. A set of experiments were conducted to explore the design space of the proposed NoC router using different values of key router parameters: channel width (flit size), arbitration scheme and IP-core-to-router mapping strategy. Area and latency results from the experiments are presented and analyzed

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Implementation of FPGA-based Multi-Standard Software Radio Receiver
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

The objective of the project was to design and implement FPGA-based Multi-standard Software Radio Receiver. WLAN and UMTS are taken as case study. Xilinx FPGA Virtex-IV is the target platform. Bandpass sampling technique at 840MHz is used to alias the combined band of WLAN and UMTS. The WLAN and UMTS channels are required at baseband with the sampling rate of 20MHz and 61.44MHz respectively. Bandpass filters are used to separate the UMTS and WLAN bands. In the channelization process, in contrast to conventional channelizer, polyphase channelizer is used. In the simulations, optimal-method-based FIR filters are used. In polyphase channelizers, the prototype filter for WLAN has 50 taps, partitioned into 5 polyphase sub-filters whereas the prototype filter for UMTS has 2520 taps, partitioned into 210 polyphase sub-filters. The received channels at baseband has 50dB of dynamic range. In the implementation, different structures for polyphase channelizer are considered (such as) standard structure, symmetricproperty based structure, Adder shared structure and serial polyphase structure with serial and parallel MAC. Serial polyphase structure with parallel MAC is selected. In the individual sub-filter implementation, different implementation structures are considered. These being Parallel Multipliers and Accumulate, Bit systolic array, Distributed Arithmetic (DA), Fast FIR, Frequency domain filtering and Multiplier-Less filtering techniques. An analysis based on the approximations for the area requirements for multipliers, adders and registers for these structures is performed. For 16-tap filter, the structures for Parallel-Multiply and accumulate, DA, Fast FIR and Frequency domain filtering require 2896 (without adders), 3072, 4064, and 5572 slices, respectively. The DA is found to be suitable for the implementation due to being resource efficient. Polyphase sub-filter is implemented with Distributed Arithmetic structure or with Xilinx-DSP48 slices for improved performance

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Rapid Prototyping of Embedded Systems Using FPGAs
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

The objectives of the project were to review developments in embedded system design and future trends, and to explore board-level rapid prototyping using FPGAs. The embedded process design flow consists of many important steps that make it essential to achieve a functioning final product within the allocated design time. In order to make appropriate decisions, embedded systems hardware and software knowledge is an important requirement. The embedded hardware decisions are analyzed in terms of processor, memory, and peripheral requirements and limitations. The embedded software process is reviewed as well as the necessary considerations to be made by the designer. The rapid prototyping strategy and the board-level prototyping method are described as a significant piece of the embedded system design flow. As an addition to simulation, prototyping provides functional and performance verification. The development platforms that were researched are the Altera DE2 board and the Xilinx Microblaze and PowerPC FX12 Development Kit. A test application was designed following the principles of embedded system design and development. The future of embedded systems greatly shifts from system on board to system on silicon and designers have to take into account different limitations. With many-core processors emerging, designers need to be able to reach peak performance by utilizing the full potential of many cores