مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Real-Time Traffic Sign Recognition System on FPGA
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

In this thesis, a new algorithm is proposed for the recognition of triangular, circular and rectangular traffic signs and it is implemented on an FPGA platform. The system can recognize 32 different traffic signs with high recognition accuracy. In the proposed method, first the image is segmented into red and blue regions, and according to the area of the each segment, the dominant color is decided. Then, Laplacian of Gaussian (LoG) based edge detection is applied to the segmented image which is followed by Hough Transform for shape extraction. Then, recognition based on Informative Pixel Percentage (IPP) matching is executed on the extracted shapes. The Traffic Sign Recognition (TSR) system is implemented on Virtex 5 FX70T FPGA, which has an embedded PPC440 processor. Some modules of TSR algorithm are designed in the FPGA logic while remaining modules are designed in the PPC440 processor. Work division between FPGA and PPC440 is carried out considering their capabilities and shortcomings of FPGA and processor. Benefits of using an FPGA with an embedded processor are exploited to optimize the system

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA-based True Random Number Generators for Embedded Cryptographic Applications
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

This thesis deals with possible ways of TRNG implementation into embedded digital hardware. Particularly, the main objective is to highlight FPGA as a considerable platform for TRNG synthesis for cryptographic purposes. Generally, it is not trivial task because FPGAs are not designed for this purpose. This work shows where one can find random processes in the FPGA and how to extract digital random data from them as well as how to enhance its statistical properties by correctors. Next objective of this work is to describe developed statistical and entropy tests for evaluating correct functionality and quality of the output bit-stream. Further, the work summarizes existing TRNG principles and designs suitable for FPGAs which appear much more rare in the literature in comparison to TRNG designs suitable for ASICs or traditional discrete electronics. Finally, the possible Ph.D theses are proposed

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Development of an FPGA-based True Random Number Generator for Space Applications
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Random numbers are required for cryptographic applications such as IT security products, smart cards etc. Hardware based random number generators are widely employed. Cryptographic algorithms are implemented on Field Programmable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) employed for space application was designed, investigated and evaluated. Several cryptographic requirements has to be satisfied for the random numbers. Two different noise sources was designed and implemented on the FPGA. The first design was based on ring oscillators as a noise source. The second design was based on astable oscillators developed on a separate hardware board and interfaced with the FPGA as another noise source. The main aim of the project was to analyse the important requirement of independent noise source on a physical level. Jitter from the oscillators being the source for the randomness, was analysed on both the noise sources. The generated random sequences was finally subjected to statistical tests

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: 2D Digital Filter Implementation on an FPGA
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

The use of two dimensional (2D) digital filters for real-time 2D data processing has found important practical applications in many areas, such as aerial surveillance, satellite imaging and pattern recognition. In the case of military operations, real-time image processing is extensively used in target acquisition and tracking, automatic target recognition and identification, and guidance of autonomous robots. Furthermore, equal opportunities exist in civil industries such as vacuum cleaner path recognition and mapping and car collision detection and avoidance. Many of these applications require dedicated hardware for signal processing. It is not efficient to implement 2D digital filters using a single processor for real-time applications due to the large amount of data. A multiprocessor implementation can be used in order to reduce processing time. Previous work explored several realizations of 2D denominator separable digital filters with minimal throughput delay by utilizing parallel processors. It was shown that regardless of the order of the filter, a throughput delay of one adder and one multiplier can be achieved. The proposed realizations have high regularity due to the nature of the processors. In this thesis, all four realizations are implemented in a Field Programming Gate Array (FPGA) with floating point adders, multipliers and shift registers. The implementation details and design trade-offs are discussed. Simulation results in terms of performance, area and power are compared. From the experimental results, realization four is the ideal candidate for implementation on an Application Specific Integrated Circuit (ASIC) since it has the best performance, dissipates the lowest power, and uses the least amount of logic when compared to other realizations of the same filter size. For a filter size of 5 x 5, realization four can produce a throughput of 16.3 million pixels per second, which is comparable to realization one and about 34% increase in performance compared to realization one and two. For the given filter size, realization four dissipates the same amount of dynamic power as realization one, and roughly 54% less than realization three and 140% less than realization two. Furthermore, area reduction can be applied by converting floating point algorithms to fixed point algorithms. Alternatively, the de-normalization and normalization stage of the floating point pipeline can be eliminated and fused together in order to save hardware resources

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Modeling and Reduction of Dynamic Power in Field-Programmable Gate Arrays
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated by ACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by 17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Lexicographic Path Searches for FPGA Routing
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

This dissertation reports on studies of the application of lexicographic graph searches to solve problems in FPGA detailed routing. Our contributions include the derivation of iteration limits for scalar implementations of negotiation congestion for standard floating point types and the identification of pathological cases for path choice. In the study of the routability-driven detailed FPGA routing problem, we show universal detailed routability is NP-complete based on a related proof by Lee and Wong. We describe the design of a lexicographic composition operator of totally-ordered monoids as path cost metrics and show its optimality under an adapted A* search. Our new router, CornNC, based on lexicographic composition of congestion and wirelength, established a new minimum track count for the FPGA Place and Route Challenge. For the problem of long-path timingdriven FPGA detailed routing, we show that long-path budgeted detailed routability is NP-complete by reduction to universal detailed routability. We generalise the lexicographic composition to any finite length and verify its optimality under A* search. The application of the timing budget solution of Ghiasi et al. is used to solve the long-path timing budget problem for FPGA connections. Our delay-clamped spiral lexicographic composition design, SpiralRoute, ensures connection based budgets are always met, thus achieves timing closure when it successfully routes. For 113 test routing instances derived from standard benchmarks, SpiralRoute found 13 routable instances with timing closure that were unroutable by a scalar negotiated congestion router and achieved timing closure in another 27 cases when the scalar router did not, at the expense of increased runtime. We also study techniques to improve SpiralRoute runtimes, including a data structure of a trie augmented by data stacks for minimum element retrieval, and the technique of step tomonoid elimination in reducing the retrieval depth in a trie of stacks structure

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: CAD Algorithms and Performance of Malibu: An FPGA with Time-Multiplexed Coarse-Grained Elements
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Modern Field-Programmable Gate Arrays (FPGAs) are used to implement a wide range of ever-larger circuits, many of which have both coarse-grained and fine-grained components. Past research into coarse-grained FPGAs optimized for such circuits have only demonstrated a 10% density advantage. In contrast, time-multiplexing of fine-grained FPGAs has demonstrated a 14x density improvement. This leaves an open question whether a time-multiplexed, coarse-grained FPGA can provide a similar density advantage. Even more important is whether the coarse-grained circuit structure can be exploited by Computer-Aided Design (CAD) tools to significantly reduce compile times. This thesis investigates a new type of FPGA in which coarse-grained, time-multiplexed resources are added to a traditional FPGA. Through time-multiplexing, density and compile time are improved. By retaining the fine-grained logic and routing resources, performance does not suffer as much as in past attempts. This thesis also presents two CAD flows, M-CAD and M-HOT, to compile Verilog for this new FPGA. Both flows speed up compile times by more than 10x, which has not been demonstrated with any other flow (even flows that sacrifice quality). They can also achieve a circuit density greater than modern FPGAs, and can trade density for performance, something most FPGA CAD flows cannot do. At maximum density, the M-HOT flow achieves a 26.1x compile time speedup, 2.5x the density, and 0.5x the performance of a commercial FPGA and CAD tool. At maximum performance, M-HOT achieves 1.0x density, and 0.7x performance. In contrast, M-CAD is a bit faster than M-HOT but achieves a lower quality result. In M-CAD, there are situations where the placer needs temporal information from the scheduler to make good decisions. Instead, M-HOT divides the circuit into heights to keep the integrated placement, routing, and scheduling problem tractable, but compile time suffers if there are too few heights. Although we show there is at most a theoretical 1.6x or 2.0x clock frequency improvement still remaining in M-HOT or M-CAD, respectively, the amount achievable may be far less. Future work should focus on improving the front-end synthesis, the coarse/fine-grained interface, and the coarse/fine-grained partitioning to provide higher quality input to the back-end CAD flow

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Design and Implementation of FPGA-Based Systems - A Review
نوع فایل: Survey
سال انتشار: 2009
چکیده:

This paper reviews the state of the art of field programmable gate array (FPGA) with the focus on FPGA-based systems. The paper starts with an overview of FPGA in the previous literature, after that starts to get an idea about FPGA programming. FPGA-based neural networks also provided in this paper in order to highlight the best advantage by using FPGA with this type of intelligent systems, and a survey of FPGA-based control systems design with different applications. In this paper, we focus on the main differences between software-based systems with respect to FPGA-based systems, and the main features for FPGA technology and its real-time applications. FPGA-based robotics systems design also provided in this review, finally, the most popular simulation results with FPGA design and implementations are highlighted

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: A Scalable Parallel Architecture with FPGA-Based Network Processor for Scientific Computing
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Several problems in scientific computing require surprisingly large computing power which current HPC commercial systems cannot deliver. In these cases the development of application-driven machines has to be taken into account since it can be the only viable and rewarding approach. From the computational point of view, one of the most challenging scientific areas is the Lattice Quantum Chromodynamics (LQCD), the discretized and computer-friendly version of Quantum Chromodynamics (QCD). QCD is the fundamental quantum theory of strong interactions. It describes the behavior of the elementary constituents of matter (the quarks) that are building blocks of stable elementary particles, such as the proton and the neutron, and of a wealth of other particles studied in high-energy physics experiments

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Stream Computing on FPGAs
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Field Programmable Gate Arrays (FPGAs) are programmable logic devices used for the implementation of a wide range of digital systems. In recent years, there has been an increasing interest in design methodologies that allow high-level design descriptions to be automatically implemented in FPGAs. This thesis describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook, and is based on the existing Brook and GPU Brook languages, which target streaming multiprocessors and graphics processing units (GPUs), respectively. A streaming language is suitable for targeting FPGAs because it allows system designers to express applications in a way that exposes parallelism, which can then be exploited through parallel hardware implementation. FPGA Brook supports replication, which allows the system designer to trade-off area for performance, by specifying the parts of an application that should be implemented as multiple hardware units operating in parallel, to achieve desired application throughput. Hardware units are interconnected through FIFO buffers, which effectively utilize the small memory modules available in FPGAs. The FPGA Brook design flow uses a source-to-source compiler, and combines it with a commercial behavioral synthesis tool to generate hardware. The source-to-source compiler was developed as a part of this thesis and includes novel algorithms for implementation of complex reductions in FPGAs. The design flow is fully automated and presents a user-interface similar to traditional software compilers. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results show that applications implemented using our flow achieve much higher throughput than the Nios II soft processor implemented in the same FPGA device. Comparison to the commercial C2H compiler from Altera shows that while simple applications can be effectively implemented using the C2H compiler, complex applications achieve significantly better throughput when implemented by our system. Performance of many applications implemented using our design flow would scale further if a larger FPGA device were used. The thesis demonstrates that using an automated design flow to implement streaming applications in FPGAs is a promising methodology

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Routing Architecture and Layout Synthesis for Multi-FPGA Systems
نوع فایل: پایان نامه
سال انتشار: 1999
چکیده:

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture, which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. This dissertation provides new insight into the strengths and the weaknesses of two popular existing routing architectures: the Partial Crossbar and the Mesh. New hybrid architectures, that use a mixture of hardwired and programmable connections, are proposed. The new architectures are the Hybrid Torus Partial-Crossbar (HTP), the Hybrid Complete-Graph Partial-Crossbar (HCGP) and the Hardwired Clusters Partial Crossbar (HWCP). We evaluate and compare several MFS routing architectures by using a rigorous experimental approach that employs real benchmark circuits. The circuits are mapped into the architectures using a customized set of partitioning, placement and inter-chip routing tools. The architectures are compared on the basis of cost (the total number of pins required in the system) and speed (determined by the post-inter-chip routing critical path delay). The key parameters associated with the partial crossbar and the hybrid architectures are explored. For the partial crossbar, the effect of varying the number of pins per subset (Pt), on the routability, speed, and cost is minor. For the hybrid architectures, a key parameter, the percentage of programmable connections (Pp), is explored and we experimentally determined that Pp = 60% gives good routability across all the benchmark circuits. We show that the Partial Crossbar is superior to the 8-way Mesh architecture. We show that one of the newly proposed hybrid architectures, HCGP, is superior to the Partial Crossbar. The HTP architecture is shown to be inferior to the HCGP and only marginally better than the Partial Crossbar. The HWCP architecture is evaluated compared to the HCGP architecture and gives encouraging routability and speed results. Overall, the results show that for single board MFSs, the HCGP is the best among all the MFS routing architectures evaluated

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: A Parallel Programming Model for a Multi-FPGA Multiprocessor Machine
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

Recent research has shown that FPGAs can execute certain applications significantly faster than state-of-the-art processors. The penalty is the loss of generality, but the reconfigurability of FPGAs allows them to be reprogrammed for other applications. Therefore, an efficient programming model and a flexible design flow are paramount for FPGA technology to be more widely accepted. In this thesis, a lightweight subset implementation of the MPI standard, called TMD-MPI, is presented. TMD-MPI provides a programming model capable of using multiple-FPGAs and embedded processors while hiding hardware complexities from the programmer, facilitating the development of parallel code and promoting code portability. A message-passing engine (TMD-MPE) is also developed to encapsulate the TMD-MPI functionality in hardware. TMD-MPE enables the communication between hardware engines and embedded processors. In addition, a Network-on-Chip is designed to enable intra-FPGA and inter-FPGA communications. Together, TMD-MPI, TMD-MPE and the network provide a flexible design flow for Multiprocessor System-on-Chip design

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Design of Timer for Application in ATM Using VHDL and FPGA
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

A watchdog timer is a computer hardware timing device that triggers a system reset if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog (writing a “service pulse” to it, also referred to as “petting the dog&rdquo. The intention is to bring the system back from the hung state into normal operation. Such a timer has got various important applications, one of them being in ATMs (Automated Teller Machine) which we have studied and designed in our project

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Sparse Matrix Sparse Vector Multiplication using Parallel and Reconfigurable Computing
نوع فایل: پایان نامه
سال انتشار: 2004
چکیده:

The purpose of this thesis is to provide analysis and insight into the implementation of sparse matrix sparse vector multiplication on a reconfigurable parallel computing platform. Common implementations of sparse matrix sparse vector multiplication are completed by unary processors or parallel platforms today. Unary processor implementations are limited by their sequential solution of the problem while parallel implementations suffer from communication delays and load balancing issues when preprocessing techniques are not used or unavailable. By exploiting the deficiencies in sparse matrix sparse vector multiplication on a typical unary processor as an strength of parallelism on an Field Programmable Gate Array (FPGA), the potential performance improvements and tradeoffs for shifting the operation to hardware assisted implementation will be evaluated. This will simply be accomplished through multiple collaborating processes designed on an FPGA

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Energy, Area and Speed Optimized Signal Processing on FPGA
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

Matrix multiplication and Fast Fourier transform are two computational intensive DSP functions widely used as kernel operations in the applications such as graphics, imaging and wireless communication. Traditionally the performance metrics for signal processing has been latency and throughput. Energy efficiency has become increasingly important with proliferation of portable mobile devices as in software defined radio. A FPGA based system is a viable solution for requirement of adaptability and high computational power. But one limitation in FPGA is the limitation of resources. So there is need for optimization between energy, area and latency. There are numerous ways to map an algorithm to FPGA. So for the process of optimization the parameters must be determined by low level simulation of each of the designs possible which gives rise to vast time consumption. So there is need for a high level energy model in which parameters can be determined at algorithm and architectural level rather than low level simulation. In this dissertation matrix multiplication algorithms are implemented with pipelining and parallel processing features to increase throughput and reduce latency thereby reduce the energy dissipation. But it increases area by the increased numbers of processing elements. The major area of the design is used by multiplier which further increases with increase in input word width which is difficult for VLSI implementation. So a word width decomposition technique is used with these algorithms to keep the size of multipliers fixed irrespective of the width of input data. FFT algorithms are implemented with pipelining to increase throughput. To reduce energy and area due to the complex multipliers used in the design for multiplication with twiddle factors, distributed arithmetic is used to provide multiplier less architecture. To compensate speed performance parallel distributed arithmetic models are used. This dissertation also proposes method of optimization of the parameters at high level for these two kernel applications by constructing a high level energy model using specified algorithms and architectures. Results obtained from the model are compared with those obtained from low level simulation for estimation of error