مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Construction of FPGA-based Test Bench for QAM Modulators
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

In today’s fast evolving mobile communications the requirements of higher data rates are continuously increasing, pushing operators to upgrade the back haul to support these speeds. A cost effective way of doing this is by using microwave links between base stations, but as the requirements of data rates increase, the capacity of the microwave links must be increased. This thesis was part of a funded research project with the objective of developing the next generation high speed microwave links for the E-band. In the research project there was a need for a testing system that was able to generate a series of test signals with selectable QAM modulations and adjustable properties to be able to measure and evaluate hardware within the research project. The developed system was designed in a digital domain using an FPGA platform from Altera, and had the ability of selecting several types of modulations and changing the properties of the output signals as requested. By using simulation in several steps and measurements of the complete system the functionality was verified and the system was delivered to the research project successfully. The developed system can be used to test several different modulators in other projects as well and is easily extended to provide further properties

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA-based Digital Phase-Locked Loop Analysis and Implementation
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to synthesize analog output, the frequency of which is controlled digitally by the FPGA. This system is implemented in a way that makes it educational and suitable for a lab module. Unlike purely digital PLL, this project involves several analog circuits soldered on PCBs, which will help the students visualize the signal flow in the PLL and get some exposure to mixed-signal systems

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Data Acquisition via RS-232 and Universal Serial Bus (USB) from an FPGA
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

The Field Programmable Gate Array (FPGA) offers a flexible solution for transferring data obtained from hardware to a PC for analysis and storage. Traditionally, an RS-232 serial interface is used to connect hardware to the PC. The RS-232 protocol is straightforward to implement with minimum hardware support. However, the presence of the Universal Serial Bus (USB) protocol has largely replaced traditional RS-232 communications, mainly due to a higher data rate and ease of configuration. In this thesis, models for the FPGA to send data in memory via RS-232 and USB were developed, as well as programs on the PC to accept those data streams. By using timing alone (no bidirectional communication), the RS-232 model could send data up to 36.9 kbps where as the USB model achieved a data rate of 702.6 kbps. By using the TXE pin and writing data only when the chip was ready, a 3.17 Mbps transfer rate was achieved

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An FPGA-based 5 Gbit/s D-QPSK Modem
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

E-band (71-76 GHz and 81-86 GHz) is permitted worldwide for ultra high capacity point-to-point (P2P) communications. The 10 GHz spectrum represents by far the widest bandwidth ever allocated for radio P2P links, enabling fiber-like transmission with data rates of gigabit per second (Gbps) and greater that are difficult to reach using the bandwidth-limited, lower microwave frequency bands. The goal of this project is to develop a Differential Quadrature Phase Shift Keying (D-QPSK) modem supporting 5 Gbps (Gigabits per second) data rate transmission. A 2.5 Gbps field programmable gate array (FPGA)-based modem had been designed and verified previously. This modem was built using FPGA and microwave components, in which the FPGA is programmed to generate a D-QPSK signal and the microwave components perform the up-and down-conversion between base-band and intermediate frequency (IF) signal. However, it is not a trivial task at all to upgrade the modem to 5 Gbps, since there are severe limitations with the FPGA solution to support the required data rate. In this thesis, a prefix parallel layer (PPL) algorithm is proposed to increase the speed of differential coding process. This algorithm can be implemented in a FPGA and it is capable for processing data rate of 5 Gbps and higher. In addition, the demodulator structure is simplified, which also raise the capability of detecting higher data rate D-QPSK signal. The 5 Gbps D-QPSK is tested the in lab environment and at the end of the project the system has successfully achieved error-free transmission. However, improvements in several aspects are needed to turn this proof-of-concept experiment into prototype for products

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA based Data Acquisition and Digital Pulse Processing for PET and SPECT
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

The most important aspects of nuclear medicine imaging systems such as Positron Emission Tomography (PET) or Single Photon Emission Computed Tomography (SPECT) are the spatial resolution and the sensitivity (detector efficiency in combination with the geometric efficiency). Considerable efforts have been spent during the last two decades in improving the resolution and the efficiency by developing new detectors. Our proposed improvement technique is focused on the readout and electronics. Instead of using traditional pulse height analysis techniques we propose using free running digital sampling by replacing the analog readout and acquisition electronics with fully digital programmable systems. This thesis describes a fully digital data acquisition system for KS/SU SPECT, new algorithms for high resolution timing for PET, and modular FPGA based decentralized data acquisition system with optimal timing and energy. The necessary signal processing algorithms for energy assessment and high resolution timing are developed and evaluated. The implementation of the algorithms in field programmable gate arrays (FPGAs) and digital signal processors (DSP) is also covered. Finally, modular decentralized digital data acquisition systems based on FPGAs and Ethernet are described

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Towards a General Framework for FPGA Based Image Processing using Hardware Skeletons
نوع فایل: Survey
سال انتشار: --
چکیده:

In this paper, we present our approach to developing a general framework for FPGA based Image Processing. This framework is based on a library of Hardware Skeletons. A hardware skeleton is a parameterized description of a task-specific architecture. A skeleton’s implementation will apply optimizations specific to the target hardware. The library normally contains a range of alternative skeletons for the same task, perhaps tailored for different data representations. The library also contains high level skeletons for compound operations, whose implementation can apply appropriate optimizations. Given a complete algorithm description in terms of skeletons, an efficient hardware configuration is generated automatically. We have developed a library of hardware skeletons for common image processing tasks, with optimized implementations specifically for Xilinx XC4000 FPGAs. This paper presents and illustrates our hardware skeleton approach in the context of some common image processing tasks. It demonstrates our approach to the broader problem of achieving optimized hardware configurations while retaining the convenience and rapid development cycle of an application-oriented, high level programming model

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design Issues in VLSI Implementation of Image Processing Hardware Accelerators
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

With the increasing capacity in today’s hardware systems enabled by technology scaling, image processing algorithms with substantially higher complexity can be implemented on a single chip enabling real-time performance. Combined with the demand for low power consumption or larger resolution seen in many applications such as mobile devices and HDTV, new design methodologies and hardware architectures are constantly called for to bridge the gap between designers productivity and what the technology can offer. This thesis tries to address several issues commonly encountered in the implementations of real-time image processing system designs. Two implementations are presented to focus on different design issues in hardware design for image processing systems. In the first part, a real-time video surveillance system is presented by combining five papers. The segmentation unit is part of a real-time automated video surveillance system developed at the department, aiming for tracking people in an indoor environment. Alternative segmentation algorithms are elaborated, and various modifications to the selected segmentation algorithm is made aiming for potential hardware efficiency. In order to bridge the memory bandwidth issue which is identified as the bottleneck of the segmentation unit, combined memory bandwidth reduction schemes with pixel locality and word-length reduction are utilized, resulting in an over 70% memory bandwidth reduction. Together with morphology, labeling and tracking units developed by two other Ph.D. students, the whole surveillance system is prototyped on an Xilinx VirtexII pro VP30 FPGA, with a real-time performance at a frame rate of 25 fps with a resolution of 320 × 240. For the second part, two papers are extended to discuss issues of a controller design and the implementation of control intensive algorithms. To avoid tedious and error prone procedure of hand coding FSMs in VHDL, a controller synthesis tool is modified to automate a controller design flow from C-like control algorithm specification to controller implementation in VHDL. To address issues of memory bandwidth as well as power consumptions, a three level of memory hierarchy is implemented, resulting in off-chip memory bandwidth reduction from N2 per clock cycle to only 1 per pixel operation. Furthermore, potential power consumption reduction of over 2.5 times can be obtained with the architecture. Together with a controller synthesized from the developed tool, a real-time image convolution system is implemented on an Xilinx VirtexE FPGA platform

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: VERTIPH : A Visual Environment for Real-time Image Processing on Hardware
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

This thesis presents VERTIPH, a visual programming language for the development of image processing algorithms on FPGA hardware. The research began with an examination of the whole design cycle, with a view to identifying requirements for implementing image processing on FPGAs. Based on this analysis, a design process was developed where a selected software algorithm is matched to a hardware architecture tailor made for its implementation. The algorithm and architecture are then transformed into an FPGA suitable design. It was found that in most cases the most efficient mapping for image processing algorithms is to use a streamed processing approach. This constrains how data is presented and requires most existing algorithms to be extensively modified. Therefore, the resultant designs are heavily streamed and pipelined. A visual notation was developed to complement this design process, as both streaming and pipelining can be well represented by data flow visual languages. The notation has three views each of which represents and supports a different part of the design process. An architecture view gives an overview of the design's main blocks and their interconnections. A computational view represents lower-level details by representing each block by a set of computational expressions and low-level controls. This includes a novel visual representation of pipelining that simplifies latency analysis, multiphase design, priming, flushing and stalling, and the detection of sequencing errors. A scheduling view adds a state machine for high-level control of processing blocks. This extended state objects to allow for the priming and flushing of pipelined operations. User evaluations of an implementation of the key parts of this language (the architecture view and the computational view) found that both were generally good visualizations and aided in design (especially the type interface, pipeline and control notations). The user evaluations provided several suggestions for the improvement of the language, and in particular the evaluators would have preferred to use the diagrams as a verification tool for a textual representation rather than as the primary data capture mechanism. A cognitive dimensions analysis showed that the language scores highly for thirteen of the twenty dimensions considered, particularly those related to making details of the design clearer to the developer

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
نوع فایل: پایان نامه
سال انشار: 2006
چکیده:

In this thesis, a both method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance. Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS – is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

A web server is a computer program that delivers (serves) content, such as web pages, to the Clients. A field-programmable gate array (FPGA) is an integrated circuit designed to be Configured by the customer or designer. We are aiming at implementing a web server using the FPGA development board (DE 270). Implementation of web server can be done by first instantiating a Nios II system in the board. Nios II system can be build around the altera’s Nios II processor using the SOPC builder tool of the quartus II CAD tool. The SOPC builder tool generates the VHDL code of the defined system. The developed code can be configured in the FPGA board to instantiate the system. After implementing the Nios II system, an application program can be run in the system to implement the web server

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Robust Speech Recognition using Speech Enhancement
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Automatic Speech Recognition (ASR) has matured into a technology which is becoming more common in our everyday lives, and is emerging as a necessity to minimise driver distraction when operating in-car systems such as navigation and infotainment. In “noise-free” environments, word recognition performance of these systems has been shown to approach 100%, however this performance degrades rapidly as the level of background noise is increased. Speech enhancement is a popular method for making ASR systems more robust. Single-channel spectral subtraction was originally designed to improve human speech intelligibility and many attempts have been made to optimise this algorithm in terms of signal-based metrics such as maximised Signal-to-Noise Ratio (SNR) or minimised speech distortion. Such metrics are used to assess enhancement performance for intelligibility not speech recognition, therefore making them sub-optimal ASR applications. This research investigates two methods for closely coupling subtractive-type enhancement algorithms with ASR: (a) a computationally-efficient Mel-filterbank noise subtraction technique based on likelihood-maximisation (LIMA), and (b) introducing phase spectrum information to enable spectral subtraction in the complex frequency domain. Likelihood-maximisation uses gradient-descent to optimise parameters of the enhancement algorithm to best fit the acoustic speech model given a word sequence known a priori. Whilst this technique is shown to improve the ASR word accuracy performance, it is also identified to be particularly sensitive to non-noise mismatches between the training and testing data. Phase information has long been ignored in spectral subtraction as it is deemed to have little effect on human intelligibility. In this work it is shown that phase information is important in obtaining highly accurate estimates of clean speech magnitudes which are typically used in ASR feature extraction. Phase Estimation via Delay Projection is proposed based on the stationarity of sinusoidal signals, and demonstrates the potential to produce improvements in ASR word accuracy in a wide range of SNR. Throughout the dissertation, consideration is given to practical implementation in vehicular environments which resulted in two novel contributions – a LIMA framework which takes advantage of the grounding procedure common to speech dialogue systems, and a resource-saving formulation of frequency-domain spectral subtraction for realisation in field-programmable gate array hardware. The techniques proposed in this dissertation were evaluated using the Australian English In-Car Speech Corpus which was collected as part of this work. This database is the first of its kind within Australia and captures real in-car speech of 50 native Australian speakers in seven driving conditions common to Australian environments

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A Dynamically Reconfigurable FPGA-based Content Addressable Memory for IP Characterization
نوع فایل: پایان نامه
سال انتشار: 2000
چکیده:

IP characterization is the process of classifying IP packets into groups depending on information in the header. In this report three implementations of FPGA-based dynamically reconfigurable Content Addressable Memories (CAMs) are described for Internet Protocol Version 6v characterization. These CAMs are characterized by a large width of the search word, a relatively small number of CAM words and the fact that these may contain ‘don’t cares’. To implement the CAMs, the CAM words were divided into a number of reconfigurable match blocks. In the first CAM implementation called the fixed length CAM, the number of these blocks is equal for all words. A more advanced architecture was developed as well, where blocks that merely store ‘don’t cares’ are omitted which leads to a varying number of reconfigurable blocks for each word. By placing these blocks in a smart way, more CAM words can be stored. This CAM is referred to as variable length CAM. In the last implementation an explicit priority mechanism was added where the priority can be programmed for each CAM word. This eliminates the slow insertion and deletion times without adding significant additional hardware costs. The CAMs were implemented on a Xilinx Virtex FPGA and the reconfiguration of the device is done dynamically from a Java environment. A user interface for changing the contents of the CAM was developed, together with a hardware interface to let the software communicate with the FPGA. It has been shown that using this technology, a CAM containing over 100 words of 320 bits can be implemented, that is able to perform more than 7 million look ups per second

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA-based Digital Phased-Locked Loop Analysis and Implementation
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to synthesize analog output, the frequency of which is controlled digitally by the FPGA. This system is implemented in a way that makes it educational and suitable for a lab module. Unlike purely digital PLL, this project involves several analog circuits soldered on PCBs, which will help the students visualize the signal flow in the PLL and get some exposure to mixed-signal systems

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Reconfigurable Design For Pattern Recognition Using Field Programmable Gate Arrays
نوع فایل: پایان نامه
سال انتشار: 1999
چکیده:

Pattern recognition techniques are often an important component of intelligent systems and are used for both data pre-processing and decision making. Broadly speaking, pattern recognition is the science that concerns the description or classification (recognition) of
measurements. The following enumerates a few of the areas where pattern recognition finds its application, such as . . . Read in DETAILS

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Speech Recognition Using FPGA Technology
نوع فایل: Technical Report
سال انتشار: 2007
چکیده:

An increasingly popular way to interact with machines is to simply talk to them. However, there is often a trade-off between ease of use and system complexity. Thus, the main objective of this project is to design and implement a speech recognition system using a Field Programmable Gate Array (FPGA). It must be capable of accurately identifying a single sound while remaining simple and fast. For this purpose, an algorithm is prototyped and tested using MATLAB™, before being implemented on an Altera DE2 board. Complications in acquiring a Fast Fourier Transform (FFT) module lead to a partial, yet functional hardware implementation