مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of a Direction Finding Algorithm on an FPGA Platform
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

In this thesis work, the implementations of the monopulse amplitude comparison and phase comparison DF algorithms are performed on an FPGA platform. After the mathematical formulation of the algorithms using maximum-likelihood approach is done, software simulations are carried out to validate and find the DF accuracies of the algorithms under various conditions. Then the algorithms are implemented on an FPGA platform by utilizing platform specific software tools. Block diagrams of the hardware implementations are given and explained in detail. Then simulations of hardware implementation of both algorithms are performed. Using the results of the simulations, DF accuracies under certain conditions are evaluated and compared to software simulations results

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Low-Cost Hardware Profiling of Run-Time and Energy in FPGA Soft Processors
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Field Programmable Gate Arrays (FPGAs) are a reconfigurable hardware platform which enable the acceleration of software code through the use of custom-hardware circuits. Complex systems combining processors with programmable logic require partitioning to decide which code segments to accelerate. This thesis provides tools to help determine which software code sections would most benefit from hardware acceleration. A low-overhead profiling architecture, called LEAP, is proposed to attain real-time profiles of an FPGA-based processor. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated and implemented to identify candidate software for acceleration. 1) Cycle profiling determines the most time-consuming functions to maximize speedup. 2) Cache stall profiling detects memory-intensive code; large memory overheads reduce the benefits of acceleration. 3) Energy consumption profiling detects energy-inefficient code through the use of an instruction-level power database to minimize the system’s energy consumption

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Wavelet based Image Compression Using FPGAs
نوع فایل: پایان نامه
سال انتشار: 2002
چکیده:

In this work we have studied well known state of the art image compression algorithms. These codecs are based on wavelet transforms in most cases. Their compression efficiency is widely acknowledged. The new upcoming JPEG2000 standard, e.g., will be based on wavelet transforms too. However, hardware implementations of such high performance image compressors are non trivial. In particular, the on chip memory requirements and the data transfer volume to external memory banks are tremendous. We suggest a solution which minimizes the communication time and volume to external random access memory. With negligible internal memory requirements this bottleneck can be avoided using the partitioned approach to wavelet transform images proposed in this thesis. Based on this idea we present modifications to the well known algorithm of Said and Pearlman Set Partitioning In Hierarchical Trees SPIHT to restrict the necessity of random access to the whole image to a small subimage only, which can be stored on chip. The compression performance in terms of visual property (measured with peak signal to noise ratio) compared to the original codec remains still the same or nearly the same. The computational power of the proposed circuits targeting to programmable hardware are promising. We have realized a prototype of this codec in a XC4000 Xilinx FPGA running at 40MHz which compresses images 10 times faster than a 1GHz Athlon processor. An application specific integrated circuit based on our approach should be much faster over again

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Improving the Area Efficiency of Heterogeneous FPGAs with Shadow Clusters
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

Field Programmable Gate Arrays (FPGAs) serve the microchip market for designs that need to be created quickly, in small volume, or that need to be updated in the field. FPGAs have not taken over the market for large capacity, high-volume Application-Specific Integrated Circuits (ASICs) since the FPGA cost is too high. This cost is mainly due to the large area gap between FPGAs and ASICs. One approach to improve the area efficiency of FPGAs is with the inclusion of hard “specific” circuits on the FPGA fabric. These circuits can implement functionality in designs in less silicon area, at a faster speed, and with less power consumption compared to implementing the same functionality in the programmable elements of an FPGA. Common examples include hard multipliers and hard memories. The fundamental question in FPGA architecture research is determining which hard circuits to include on an FPGA. Every included hard circuit needs to be used and provide a benefit to the range of designs mapped to FPGAs

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: A Combined Clustering and Placement Algorithm for FPGAs
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

One of the major drawbacks of reprogrammable microchips, such as field-programmable gate arrays (FPGAs), is an inherent speed disadvantage over ASIC technologies. To mitigate this speed disadvantage, this thesis presents a novel algorithm to improve timing performance at the possible expense of area and runtime. The algorithm presented leverages node duplication and a depth-optimal initial clustering to provide a starting point for a non-greedy, iterative optimization technique using detailed placement and timing information to develop the final clustering and placement solutions. For a set of benchmarks commonly used in FPGA research, the proposed algorithm achieves an 11% critical-path delay improvement compared to the VPR academic tool flow. This performance improvement is obtained at the expense of a 44% increase in area usage and a 26x increase in maximum runtime. Techniques have also been implemented to sacrifice performance to moderate the area or runtime increases. For a 1% critical-path delay penalty, the runtime can be improved by a factor of 4. The algorithm also provides facilities to impose area restrictions, in which case timing degradation is proportional to the area saved

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA-based Compensation Method for Correcting Distortion in Voltage Inverters
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

This thesis presents a method to compensate for the blanking time distortion in Space Vector Modulated (SVM) voltage source inverters. Blanking time distortion is caused by the delay inserted to prevent the short circuit that would occur if the two transistors in the same inverter leg are both on at the same time. This delay produces harmonic distortion and non-linearity when two-switch phase legs are used in inverters to generate sinusoidal voltages for various types of AC loads. The approach in this thesis uses a Field Programmable Gate Array to create a pulse by pulse compensation technique that adjusts the symmetric SVM pulses in an attempt to eliminate the voltage distortion caused by the blanking time effect. This technique is evaluated through simulation and experimental results. This thesis proves that the delay caused by the insertion of blanking time can be compensated using a Field Programmable Gate Array and that the blanking time delay is not the dominant source of the 5th and 7th lower order harmonic distortion in voltage source inverters at low voltages

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: FPGA Implementation of 802.11b MAC Controller: Transmitter
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

The 802.11 specification is a wireless LAN standard defined by IEEE in 1997. This standard defines the media access control (MAC) and physical (PHY) layers for a LAN with wireless connectivity. Now, wireless LAN is applied widely in our life, such as airports, metropolis and campus … etc. In this thesis, we used VHDL to design the wireless LAN MAC controller transmission part including MAC functions and frame format generation in 802.11b specification. We designed MAC transmitter functions with four modules and implemented hardware of MAC transmission part on Xilinx FPGA (Field Programmable Gate Array), VirtexII XC2V1000 board, then verified all of functions by logic analyzer. Finally, this design use total 6,976 equivalent gate counts and can reach the processing rate of 112.41 MHz

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Hardware/Software Codesign of MP3 Decoder with 36/32-point (I)DCT Accelerators
نوع فایل: پایان نامه
سال انتشار: 2005
چکیده:

An MP3 audio decoder is designed as System-on-a-Chip using hardware/software codesign techniques. The hardware architecture is built on the LEON SoC platform, which contained an open source SPARC-V8 architecture compatible processor, an AMBA bus. A pre-designed flash card interface hardware core is added to this system. And then an audio driver module also is added to the system. After a performance analysis to the decoder, the MP3 decoder is partitioned into software part and hardware part. The hardware parts, a 36 point IDCT decoder and a 32 point DCT decoder, are designed as two accelerators connected to AMBA. The final MP3 decoder can decode MP3 stream with the help of the 36 point IDCT accelerator and 32 point DCT accelerator

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Reducing Power in FPGA Designs Through GLITCH Reduction
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

While FPGAs provide flexibility for performing high performance DSP functions, they consume a significant amount of power. Often, a large portion of the dynamic power is wasted on unproductive signal glitches. Reducing glitching reduces dynamic energy consumption. In this study, retiming is used to reduce the unproductive energy wasted in signal glitches. Retiming can reduce energy by up to 92%. Evaluating energy consumption is an important part of energy reduction. In this work, an activity rate-based power estimation tool is introduced to provide FPGA architecture independent energy estimations at the gate level. This tool can accurately estimate power consumption to within 13% on average. This activation rate-based tool and retiming are combined in a single algorithm to reduce energy consumption of FPGA designs at the gate level. In this work, an energy evaluation metric called energy area delay is used to weigh the energy reduction and clock rate improvements gained from retiming against the area and latency costs. For a set of benchmark designs, the algorithm that combines retiming and the activation rate-based power estimator reduces power on average by 40% and improves clock rate by 54% for an average 1.1× area cost and a 1.5× latency increase

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping
نوع فایل: پایان نامه
سال انتشار: 2013
چکیده:

As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devices on critical paths forces designers to reduce clock speed in order to meet timing. For an important and emerging class of applications that target energy-minimal operation at the cost of delay, the impact of variation-induced defects at very low voltages mandates the sizing up of transistors and operation at higher voltages to maintain functionality. With post-fabrication configurability, FPGAs have the opportunity to self-measure the impact of variation, determining the speed and functionality of each individual resource. Given that information, a delay-aware router can use slow devices on non-critical paths, fast devices on critical paths, and avoid known defects. By mapping each component individually and customizing designs to a component’s unique physical characteristics, we demonstrate that we can eliminate delay margins and reduce energy margins caused by variation. To quantify the potential benefit we might gain from component-specific mapping, we first measure the margins associated with parameter variation, and then focus primarily on the energy benefits of FPGA delay-aware routing over a wide range of predictive technologies (45 nm–12 nm) for the Toronto20 benchmark set. We show that relative to delay-oblivious routing, delay-aware routing without any significant optimizations can reduce minimum energy/operation by 1.72× at 22 nm. We demonstrate how to construct an FPGA architecture specifically tailored to further increase the minimum energy savings of component-specific mapping by using the following techniques: power gating, gate sizing, interconnect sparing, and LUT remapping. With all optimizations considered we show a minimum energy/operation savings of 2.66× at 22 nm, or 1.68–2.95× when considered across 45–12 nm. As there are many challenges to measuring resource delays and mapping per chip, we discuss methods that may make component-specific mapping more practical. We demonstrate that a simpler, defect-aware routing achieves 70% of the energy savings of delay-aware routing. Finally, we show that without variation tolerance, scaling from 16 nm to 12 nm results in a net increase in minimum energy/operation; component-specific mapping, however, can extend minimum energy/operation scaling to 12 nm and possibly beyond

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Sustainable Fault-Handling of Reconfigurable Logic Using Throughput-Driven Assessment
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

A sustainable Evolvable Hardware (EH) system is developed for SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) using outlier detection and group testing-based assessment principles. The fault diagnosis methods presented herein leverage throughput-driven, relative fitness assessment to maintain resource viability autonomously. Group testing-based techniques are developed for adaptive input-driven fault isolation in FPGAs, without the need for exhaustive testing or coding-based evaluation. The techniques maintain the device operational, and when possible generate validated outputs throughout the repair process. Adaptive fault isolation methods based on discrepancy-enabled pair-wise comparisons are developed. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, a method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. The results from the analytical FPGA model are demonstrated via a self-healing, self-organizing evolvable hardware system. Reconfigurability of the SRAM-based FPGA is leveraged to identify logic resource faults which are successively excluded by group testing using alternate device configurations. This simplifies the system architect’s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance versus availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an Observer-Controller model. Results are demonstrated using a Data Encryption Standard (DES) core that occupies approximately 305 FPGA slices on a Xilinx Virtex-II Pro FPGA. With a single simulated stuck-at-fault, the system identifies a completely validated replacement configuration within three to five positive tests. The approach demonstrates a readily-implemented yet robust organic hardware application framework featuring a high degree of autonomous self-control.

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Low Energy Field-Programmable Gate Array
نوع فایل: پایان نامه
سال انتشار: 2000
چکیده:

The domain of Field-Programmable Gate Arrays (FPGAs) has undergone a dramatic revolution in the past decade. What started as a cheap alternative to custom design for implementing non-critical functions has now progressed into a new model of computation. The programmability of the device at a bit level combined with an application specific flow of data between operations offer the silicon reusability of general purpose processor with the implementation efficiency of application specific integrated circuits. One of the major drawbacks of FPGAs that has not been addressed is the poor energy efficiency. This factor has excluded the full utilization of its potential in energy sensitive domains like portable computing. Even the application domains that do not require low energy consumption will feel the consequence as the process technology moves into the sub-0.1μm region. This is because of the higher frequencies and larger chips that will be seen in the future process technologies. This work investigates the impact of the different architectural components on the overall energy consumption. The interconnect architecture, logic block structure, and the configuration technique of the FPGA is redesigned from the perspective of energy efficiency. Stand-alone and embedded FPGAs are implemented to verify the functionality and obtain performance data. Measured data show more than an order of magnitude improvement over comparable commercial devices

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: Efficient Multi-Ported Memories for FPGAs
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

Multi-ported memories are challenging to implement on FPGAs since the provided block RAMs typically have only two ports. In this dissertation we present a thorough exploration of the design space of FPGA multi-ported memories by evaluating conventional solutions to this problem, and introduce a new design that efficiently combines block RAMs into multiported memories with arbitrary numbers of read and write ports and true random access to any memory location, while achieving significantly higher operating frequencies than conventional approaches. For example we build a 256-location, 32-bit, 12-ported (4-write, 8-read) memory that operates at 281 MHz on Altera Stratix III FPGAs while consuming an area equivalent to 3679 ALMs: a 43% speed improvement and 84% area reduction over a pure ALM implementation, and a 61% speed improvement over a pure “multipumped” implementation, although the pure multipumped implementation is 7.2-fold smaller

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: FPGA-based PWM Techniques for Controlling an Inverter
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Pulse Width Modulation has nowadays become an integral part of every electronics system. These techniques have been widely accepted and are researched extensively nowadays. It has found its application in large number of applications as a voltage controller. Its use in controlling output voltage of Inverter is the most frequently used application. There are basically two main techniques of PWM Generation- Analog technique and Digital Technique. This thesis deals with these two techniques. First Analog techniques were studied in detail but these techniques have some demerits. Due to these demerits digital techniques were studied. Various digital PWM Generator topologies were studied. The VHDL code for each of these topologies was written and synthesized using Xilinx ISE 10.1 software. Behavioral Simulation was performed on the architecture and after verifying the results this VHDL code was downloaded to SPARTAN 3E FPGA. After downloading the code in FPGA real time debugging was done for the architecture. The results were seen in Chipscope Pro software. Also from Synthesis report generated after synthesizing the VHDL code of each digital PWM Generator topologies comparison was done between these topologies in terms of number of logic blocks used and device utilization of each architecture

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پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

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نام: An FPGA Implementation of Incremental Clustering for Radar Pulse De-interleaving
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Incremental clustering is the unsupervised classification of dynamic streaming data samples into related groups called clusters. The process considers each data point only once so it is applicable to real-time problems requiring low latency solutions. One such application is the deinterleaving of radar pulse streams in an electronic warfare (EW) systems. Given a single stream of combined radar signals deinterleaving attempts to identify individual radar emitters based on characteristics of the received signal. This thesis focuses on implementing an incremental clustering algorithm on a field-programmable gate array (FPGA) for the purposes of radar pulse deinterleaving. We introduce ICED, an algorithm for the Incremental Clustering of Evolving Data, and discuss the details of implementing it in an FPGA. Experimental results show the applicability of the algorithm to the real-time requirements of EW pulse deinterleaving. The resulting design provides a 16 cluster implementation that consumes 70% of a Xilinx Virtex-5 SX95T FPGA and requires a processing latency of 420ns, resulting in a 39x speedup over software