مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Implementation of an MP3 Player on an FPGA
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

This thesis has the intention to create a base for renewal of the DAT095 (Electronic System Design Project) course. As a basis for the new project, implementation of a LEON3 processor on a FPGA board was done and a MP3 player application was run on it. The MPG123 [15] applications’ source code was used and modified according to the system and by using hardware/software co-design techniques a complete system was designed. The audio interface hardware core was designed according to the requirements of the digital to analog converter MCP4288 [3]. Necessary interfaces were implemented according to the AMBA bus. A demonstrator was built on the Digilent Spartan3 xc3s1000 board [4]. During the analysis of the MP3 decoder, it was seen that the Inverse Discrete Cosine Transform (IDCT) part of the decoder algorithm was too computation-intensive and a hardware implementation for that part was made and attached to the processor’s AMBA bus as a slave. The MP3 decoder software and the IDCT hardware were working together to decode the data. Finally the development platform was changed to Digilent Atlys Spartan6 FPGA development board [21] that gave a more flexible usage for future works. The LEON3 processors template design was modified according to the needs of the new development platform and the MPG123 application was run on it

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: JPEG Image Compression Using an FPGA
نوع فایل: پایان نامه
سال انتشار: 2006
چکیده:

Image compression is an important topic in commercial, industrial, and academic applications. Whether it be in commercial photography, industrial imaging, or video, digital pixel information can comprise considerably large amounts of data. Management of such data can involve significant overhead in computational complexity, storage, and data processing. Typical access speeds for storage mediums are inversely proportional to capacity. Through data compression, such tasks can be optimized. Image and video compressors and decompressors (codecs) are implemented mainly in software as digital signal processors have optimized instruction sets to manage the required operations. Hardware-specific codecs can be integrated into digital systems fairly easily, requiring work only in the areas of interface and overall integration. Improvements in speed occur primarily because the hardware can be tailored to the compression algorithm as well as the application. Using an FPGA to implement a codec combines the best of two worlds: significantly increased processing speed due to the use of customized hardware, and flexibility to make changes and tunings of the algorithm since FPGA-based designs are easily modified. The JPEG algorithm was chosen for this project as it is well defined and highly recognizable. JPEG provides a baseline compression algorithm that can be modified in numerous ways to fit any desired application. The JPEG specification, released initially in 1991, does not specify a particular implementation. A programmable hardware platform, developed in the computer architecture laboratory at UCSB, was chosen as a substrate for this project. The baseline JPEG compression algorithm was tailored to ¯t this board, using custom hardware pipelining, as well as parallel data paths. The core compression design was created using the Verilog hardware description language. The supporting software was written in C, developed for a DSP and the PC. The implementation of this project was successful on achieving significant compression ratios. The sample images chosen showed different degrees of contrast and fine detail to show how the compression affected high frequency components within the images. The throughput of the design excelled in the FPGA core. However, inherent limitations in the interface to the FPGA limited the overall performance of the design

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Exploring networks-on-chip for FPGAs
نوع فایل: Technical Report
سال انتشار: 2013
چکیده:

Developments in fabrication processes have shifted the cost ratio between wires and transistors to allow new trade-offs between computation and communication. Rising clock speeds have lead to multi-cycle cross-chip communication and pipelined buses. It is then a small step from pipelining to switching and the development of multi-core networked systems-on-chip. Modern FPGAs are also now home to complex systems-on-chip. A change in the way we structure the computation demands a change in the way we structure the communication on-chip. This thesis looks at Network-on-Chip design for FPGAs beyond the trade-offs between hard (silicon) and soft (configurable) designs. FPGAs are capable of extremely flexible statically routed bit-based wiring, but this flexibility comes at a high area, latency and power cost. Soft NoCs are able to maintain this flexibility, but do not necessarily make good use of the computation-communication trade-off. Hard NoCs are more efficient when used, but are forced to operate below capacity by the soft IP cores. It is also difficult to design hard NoCs with the flexibility needed without wasting silicon when the network is not used. In the first part of this thesis I explore the capability of Time-Division Multiplexed (TDM) wiring to bridge the gap between the fine-grain static FPGA wiring and the bus-based dynamic routing of a NoC. By replacing some of the static FPGA wiring with TDM wiring I am able to time division multiplex hard routers and make better use of the non-configurable area. The cost of a hard network is reduced by moving some of the area cost from the routers into reusable TDM wiring components. The TDM wiring improves the interface between the hard routers and soft IP blocks which leads to higher logic density overall. I show that TDM wiring makes hard routers a flexible and efficient alternative to soft interconnect. The second part of this thesis looks at the feasibility of replacing all static wiring on the FPGA with TDM wiring. The aim was to increase the routing capacity of the FPGA whilst decreasing the area used to implement it. An ECAD flow was developed to explore the extension to which the amount of wiring can be reduced. The results were then used to design the TDM circuitry. My results show that an 80% reduction in the amount of wiring is possible though time-division multiplexing. This reduction is sufficient to increase the routing capacity of the FPGA whilst maintaining similar or better logic density. This TDM wiring can be used to implement area and power-efficient hard networks-on-chip with good flexibility, as well as improving the performance of other hard IP blocks

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Field-Programmable Gate Array Logic Synthesis Using Boolean Satisfiability
نوع فایل: پایان نامه
سال انتشار: 2005
چکیده:

Field-Programmable gate arrays (FPGAs) are reprogrammable logic chips that can be configured to implement various digital circuits. FPGAs are fast replacing custom ASICs in many areas due to their flexibility and fast turn around times for product development. However, these benefits come at a heavy cost of area, speed, and power. The FPGA architecture and technology mapping phase are fundamental in determining the performance of the FPGA. This thesis presents novel tools using Boolean satisfiability (SAT) to aid in both these areas. First, an architecture efficiency evaluation tool is developed. The tool works by reading in a description of the FPGA architecture and rates how flexible that architecture can be in implementing various circuits. Next, a novel technology mapping approach is developed and compared to current methods. This work contrasts with current approaches since it can be applied to almost any FPGA architecture. Finally, a resynthesis algorithm is described which rates the utility of current FPGA technology mappers where it can also be used to discover optimal configurations of common subcircuits to digital design

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Image Compression Using BinDCT For Dynamic Hardware FPGA’s
نوع فایل: پایان نامه
سال انتشار: 2007
چکیده:

This thesis investigates the prospect of using a Binary Discrete Cosine Transform as an integral component of an image compression system. The Discrete Cosine Transform (DCT) algorithm is well known and commonly used for image compression. Various compression techniques are actively being researched as they are attractive for many industrial applications. The particular compression technique focused on was still image compression using the DCT. The recent expansion of image compression algorithms and multimedia based mobile, including many wireless communication applications, handheld devices, digital cameras, videophones, and PDAs has furthered the need for more efficient ways to compress both digital signals and images. The objective of this research to find a generic model to be used for image compression was met. This software model uses the BinDCT algorithm and also develops a detection system that is accurate and efficient for implementation in hardware, particularly to run in real-time. This model once loaded on to any dynamic hardware should update by reconfiguring the FPGA automatically, during run time with different BinDCT processors. Such a model will enhance our understanding of the dynamic BinDCT processor in image compression. Image analysis involves examination of the image data for a specific application. The characteristic of an image decides the most efficient algorithm. Selection techniques were designed centered on use of the entropy calculation for each 8 x 8 tile. However many other techniques were analyzed such as homogeneity. Selection of the most efficient BinDCT algorithm for each tile was a challenge met by analysis of the entropy data. For the BinDCT different configurations were analyzed with standard grey scale photographic images. Upgrading the available technology to the point where the most suitable BinDCT configuration for each image tile input stream will be continuously configured all the time, will lead to significant coding advantage in image analysis and traditional compression process. Hence, great performance can be achieved if the FPGA can dynamically switch between the different configurations of the BinDCT transform

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Modular FPGA-based Software Defined Radio for CubeSats
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

Digital communications devices designed with application-specific integrated circuit (ASIC) technology suffer from one very significant limitation—the integrated circuits are not programmable. Therefore, deploying a new algorithm or an updated standard requires new hardware. Field-programmable gate arrays (FPGAs) solve this problem by introducing what is essentially reconfigurable hardware. Thus, digital communications devices designed on FPGAs are capable of accommodating multiple communications protocols without the need to deploy new hardware, and can support new protocols in a matter of seconds. In addition, FPGAs provide a means to update systems that are physical difficult to access. For these reasons, FPGAs provide us with an ideal platform for implementing adaptive communications algorithms. This thesis focuses on using FPGAs to implement an adaptive digital communications system. Using the Universal Software Radio Peripheral (USRP) as a base, this thesis aims to create a highly-adaptive, plug and play software-defined radio (SDR) that fits CubeSat form-factor satellites. Such a radio platform would enable CubeSat engineers to develop new satellites faster and with lower costs. This thesis presents a new system, the CubeSat SDR, that adapts the USRP platform to better suit the space and power limitations of a CubeSat

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Algorithm Acceleration using FPGAs
نوع فایل: پایان نامه
سال انتشار: 2004
چکیده:

Hybrid architectures consisting of a general-purpose processor and configurable logic are becoming very popular. A number of recent publications (e.g. [51], [52]) have proved efficiency of these architectures on acceleration of compute- and data-intensive applications. Similarly to these research trends, this thesis studies a potential of state of the art platform FPGAs in the field of algorithm acceleration. A simple model for a quantitative analysis of acceleration capabilities is introduced. This model is applied to the target architecture based on Xilinx MicroBlaze soft-core processor. Quality of this model is demonstrated on several simple algorithms such as a color space conversion or a discrete cosine transform. Based on the experiments, several important issues relating to the acceleration efficiency are identified. The major effect seems to have a data transfer overhead. Though, significant speedups can be still achieved over an optimized software implementation of the algorithms

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: iScope: A Touch Screen Digital Storage Oscilloscope based on System-on-Chip over FPGA Technology
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

All Electronic Engineers, at some point of their professional careers, needed to use an oscilloscope to analyze signals, provided by electronic circuitry during hardware debugging. The current digital oscilloscopes allow a wide range of operations that go beyond the digital signal processing. Nowadays, with novel oscilloscope equipments it is possible to store information directly into flash drives, to implement networks with other equipments and to schedule events, among other features. Though, there haven’t been considerable improvements with respect to interfaces. Basically these instrument’s interface is based on a panel with buttons and wheels, not being user friendly. A touch screen could bring powerful advantages for signal handling. The implementation of interactive menus on screen may help saving precious space that could be used for expanding the visible area (without having to increase the size of the equipment) and it will become possible for users to apply intuitive gestures during circuitry analysis. Having in consideration the potential improvements above differentiated, this work was centered in the development of original approaches towards the integration of technologies as well as an operating system currently used in different electronic equipments aiming the potential optimization of digital oscilloscope’s interfaces. The complete system shall be composed of a signal acquisition and conversion system that connects to the Digital Signal Processing unit. As a user interface it will be used a module containing a color TFT LCD and a capacitive touch-screen sensor. These two modules were connected to a FPGA (Field Programmable Gate Array) board where the necessary processing units and support components will be implemented as a SoC (System-on-Chip) system. Within the SoC system implemented a co-processing unit has a major role in the system optimization. An Embedded OS, i.e. Linux v2.6.x, was tailored for handling and control of all system’s components and process. All Electronic Engineers, at some point of their professional careers, needed to use an oscilloscope to analyze signals, provided by electronic circuitry during hardware debugging. The current digital oscilloscopes allow a wide range of operations that go beyond the digital signal processing. Nowadays, with novel oscilloscope equipments it is possible to store information directly into flash drives, to implement networks with other equipments and to schedule events, among other features. Though, there haven’t been considerable improvements with respect to interfaces. Basically these instrument’s interface is based on a panel with buttons and wheels, not being user friendly. A touch screen could bring powerful advantages for signal handling. The implementation of interactive menus on screen may help saving precious space that could be used for expanding the visible area (without having to increase the size of the equipment) and it will become possible for users to apply intuitive gestures during circuitry analysis. Having in consideration the potential improvements above differentiated, this work was centered in the development of original approaches towards the integration of technologies as well as an operating system currently used in different electronic equipments aiming the potential optimization of digital oscilloscope’s interfaces. The complete system shall be composed of a signal acquisition and conversion system that connects to the Digital Signal Processing unit. As a user interface it will be used a module containing a color TFT LCD and a capacitive touch-screen sensor. These two modules were connected to a FPGA (Field Programmable Gate Array) board where the necessary processing units and support components will be implemented as a SoC (System-on-Chip) system. Within the SoC system implemented a co-processing unit has a major role in the system optimization. An Embedded OS, i.e. Linux v2.6.x, was tailored for handling and control of all system’s components and process

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: WvFEv3: An FPGA-based General Purpose Digital Signal Processor for Space Applications
نوع فایل: پایان نامه
سال انتشار: 2011
چکیده:

The Waves instruments aboard the Juno and Radiation Belt Storm Probe (RBSP) spacecraft represents the next generation of space radio and plasma wave instrumentation developed by the University of Iowa’s Radio and Plasma Wave group [1, 2]. The previous generation of such instruments on the Cassini [3] spacecraft utilized several analog signal-conditioning techniques to compress and condense scientific data. Compression techniques are necessary because the plasma wave instruments can often generate significantly more science data than can be transmitted using the narrow telemetry channel of the hosting spacecraft. The next generation of plasma wave instrumentation represents a major shift of analog signal conditioning functionality to the digital domain, drastically reducing the amount of power and mass required by the instrument while simultaneously further condensing scientific data, increasing the precision of plasma emission measurements, and adding flexibility. The digital transition of Waves instruments relies heavily on available integrated circuit technologies capable of performing signal processing tasks in real time. Performance is not the only consideration, however, as the digital system must also operate in a space environment with no atmosphere, wide temperature variations, and radiation exposure for the lifetime of the mission. Architecturally speaking, the ideal solution would also be flexible enough to implement a wide variety of digital signal processing techniques for changing scenarios during space flight with the additional benefit of potentially using such a system in missions beyond Juno and RBSP. The solution presented in this thesis is to utilize a low-cost radiation tolerant field programmable gate array (FPGA) that serves as a space qualified implementation platform for a custom designed general-purpose digital signal processor, called the WvFEv3. The design of the WvFEv3 processor is unique among traditional FPGA implementations due to its generic processing flow, thus allowing a wide variety of algorithms to be implemented programmatically without the need to reprogram the FPGA during a mission. This approach addresses the performance and flexibility needs of the Waves instruments in its continuing goals to reduce mass and power while simultaneously increasing the precision and compression ratios of science products

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Object Tracking Using FPGA -- An Application to a Mobile Robot
نوع فایل: پایان نامه
سال انتشار: 2012
چکیده:

Object tracking in real time video is used to control the direction and to change the speed of a small two wheeled robot. The direction and speed of the mobile robot is controlled by tracking the position of the colored objects associated with the hand of the input user. An FPGA is used to track the position of the objects in the images generated by the digital camera. Images received by the camera are in the form of Bayer pattern which are then transformed into RGB color space. To get a binary image out of the RGB image, color space is transformed into HSV so as to improve the result of color segmentation in different light intensities. After the binary image is generated, projection histograms are used to track the positions of the objects. Different positions of the objects are associated with different instructions which are sent to the robot. The robot receives these instructions through wireless transceiver and the controller inside the robot decodes these instructions and acts accordingly. By changing the position of the objects, the robot can be moved forward with slow or high speed, stopped, turned left or right with different angles, moved in reverse direction and can be rotated clock-wise or in counter-clock wise direction

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Hardware Based Packet Filtering Using FPGAs
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

This paper seeks to understand the operation of packet filters implemented on FPGAs as high speed platforms and evaluates the suitability of FPGAs as platforms for packet filter implementation. It must be remembered that packet filters need to operate at line speeds or else they become detrimental to the health of any network they may be placed upon by introducing significant delays. This task is approached by a novice to the world of FPGAs and hardware description languages and begins with a review of other implementations of packet filters on FPGAs. The design of a simple packet filter that filters packets based upon transport protocol, IP addresses and port numbers is presented. The packet filter in this work is not realized on a FPGA device but its logical design is verified with the use of ModelSim Starter Edition. The end product of this endeavor is a kernel upon which the filter can be expanded and the reaffirmation that FPGAs are successful candidates for packet filter platforms

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Design and Implementation of an Integrated Navigation System on an FPGA
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

Inertial Navigation Systems (INS) have many applications and are important to the navigational capabilities of unmanned autonomous vehicles. Advances in low-cost inertial measurements units (IMUs) have opened the doors to the design of low-cost INS. Unfortunately, low-cost IMU technology suffers from high levels of noise and instability in their measurements. The inclusion of aiding sensors provides a way to estimate and compensate for these errors. Implementation of an aided INS on a field-programmable gate array (FPGA) provides a flexible platform the development of an aided INS. This thesis describes the design and implementation of a low-cost INS based on an FPGA processing platform and low-cost micro-electro-mechanical system (MEMS) IMU with global positioning system (GPS) unit, compass, and inclinometer aiding sensors. A simulation environment is developed for testing of the algorithms and comparison with the results of the FPGA based implementation of the system. The INS processes the inertial measurements through a mechanization algorithm to provide the position, velocity, and orientation INS outputs. The aiding data is combined with the INS using a loosely coupled Kalman filter which estimates the errors in the position, velocity, orientation, and IMU sensor bias. Simulations show that, despite the errors in the INS alone, error estimates from the Kalman filter using the aided INS configuration are able to bring the output of the INS to less than two meters of error in position. The aided INS is implemented using a Xilinx FPGA with a PowerPC processor. Outdoor testing is accomplished by attaching the FPGA system to a robotic platform. Results from outdoor testing show that the aided INS design is able exceed the two meter expected accuracy of the GPS for points along the path where the position is well known

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Efficient FPGA Implementation of Image Enhancement using Video Streams
نوع فایل: پایان نامه
سال انتشار: 2010
چکیده:

This thesis is composed of three main parts; displaying an analog composite video input by via converting to digital VGA format, license plate localization on a video image and image enhancement on FPGA. Analog composite video input, either PAL or NTSC is decoded on a video decoder board; then on FPGA, video data is converted from 4:2:2 YCbCr format to RGB. To display RGB data on the screen, line doubling deinterlacing algorithm is used since it is efficient considering computational complexity and timing. When taking timing efficiency into account, image enhancement is applied only to beneficial part of the image. In this thesis work, beneficial part of the image is considered as numbered plates. Before image enhancement process, the location of the plate on the image must be found

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Performance Driven FPGA Design With an ASIC Perspective
نوع فایل: پایان نامه
سال انتشار: 2009
چکیده:

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and weaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357 MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx’ own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools

[hess]

پاسخ : مقالات علمی معتبر , پایان نامه ها و eBook های مربوط به FPGA

سلام ..

نام: Academic Clustering and Placement Tools for Modern FPGA Architectures
نوع فایل: پایان نامه
سال انتشار: 2008
چکیده:

Academic tools have been used in many research studies to investigate Field- Programmable Gate Array (FPGA) architecture, but these tools are not sufficiently flexible to represent modern commercial devices. This thesis describes two new tools, the Dynamic Clusterer (DC) and the Dynamic Placer (DP) that perform the clustering and placement steps in the FPGA CAD flow. These tools are developed in direct extension of the popular Versatile Place and Route (VPR) academic tools. We describe the changes that are necessary to the traditional tools in order to model modern devices, and provide experimental results that show the quality of the algorithms achieved is similar to a commercial CAD tool, Quartus II. Finally, a small number of research experiments were investigated using the clustering and placement tools created to demonstrate the practical use of these tools for academic research studies of FPGA CAD tools